usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

1069

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

1093

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD,

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

1119

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_ECR, events);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

1314

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_VRRS, 1);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

132

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

1321

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_UVRS, 1);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

1372

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_GET_CONF_INTR);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

260

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_DSAL,

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

262

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_DSAH,

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

274

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_DSAL, 0);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

275

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_DSAH, 0);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

474

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

485

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

579

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

641

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

773

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_MAC_FILTERS);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

794

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_MACL, val32);

usr/src/uts/intel/io/vmxnet3s/vmxnet3_main.c

796

VMXNET3_BAR1_PUT32(dp, VMXNET3_REG_MACH, val32);