usr/src/uts/common/io/ntxn/nic_phan_reg.h

165

#define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084))

usr/src/uts/common/io/ntxn/nic_phan_reg.h

166

#define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

100

#define ISR_INT_TARGET_MASK_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

102

#define ISR_INT_VECTOR (UNM_PCIX_PS_REG(PCIX_INT_VECTOR))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

103

#define ISR_INT_MASK (UNM_PCIX_PS_REG(PCIX_INT_MASK))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

104

#define ISR_INT_STATE_REG (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

106

#define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC)))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

84

#define ISR_INT_TARGET_STATUS (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

85

#define ISR_INT_TARGET_STATUS_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

86

#define ISR_INT_TARGET_STATUS_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

87

#define ISR_INT_TARGET_STATUS_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

88

#define ISR_INT_TARGET_STATUS_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

89

#define ISR_INT_TARGET_STATUS_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

90

#define ISR_INT_TARGET_STATUS_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

91

#define ISR_INT_TARGET_STATUS_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

93

#define ISR_INT_TARGET_MASK (UNM_PCIX_PS_REG(PCIX_TARGET_MASK))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

94

#define ISR_INT_TARGET_MASK_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

95

#define ISR_INT_TARGET_MASK_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

96

#define ISR_INT_TARGET_MASK_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

97

#define ISR_INT_TARGET_MASK_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

98

#define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5))

usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

99

#define ISR_INT_TARGET_MASK_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6))

usr/src/uts/common/io/ntxn/unm_inc.h

542

#define D3_CRB_REG_FUN0 (UNM_PCIX_PS_REG(0x0084))

usr/src/uts/common/io/ntxn/unm_inc.h

543

#define D3_CRB_REG_FUN1 (UNM_PCIX_PS_REG(0x1084))

usr/src/uts/common/io/ntxn/unm_inc.h

544

#define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084))

usr/src/uts/common/io/ntxn/unm_inc.h

545

#define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084))

usr/src/uts/common/io/ntxn/unm_inc.h

548

#define ISR_I2Q_CLR_PCI_LO (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_LO))

usr/src/uts/common/io/ntxn/unm_inc.h

549

#define ISR_I2Q_CLR_PCI_HI (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_HI))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1037

#define ISR_INT_TARGET_STATUS (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1038

#define ISR_INT_TARGET_STATUS_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1039

#define ISR_INT_TARGET_STATUS_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1040

#define ISR_INT_TARGET_STATUS_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1041

#define ISR_INT_TARGET_STATUS_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1042

#define ISR_INT_TARGET_STATUS_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1043

#define ISR_INT_TARGET_STATUS_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1044

#define ISR_INT_TARGET_STATUS_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1046

#define ISR_INT_TARGET_MASK (UNM_PCIX_PS_REG(PCIX_TARGET_MASK))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1047

#define ISR_INT_TARGET_MASK_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1048

#define ISR_INT_TARGET_MASK_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1049

#define ISR_INT_TARGET_MASK_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1050

#define ISR_INT_TARGET_MASK_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1051

#define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1052

#define ISR_INT_TARGET_MASK_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1053

#define ISR_INT_TARGET_MASK_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1055

#define ISR_INT_VECTOR (UNM_PCIX_PS_REG(PCIX_INT_VECTOR))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1056

#define ISR_INT_MASK (UNM_PCIX_PS_REG(PCIX_INT_MASK))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1057

#define ISR_INT_STATE_REG (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

1059

#define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC)))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

680

#define D3_CRB_REG_FUN0 (UNM_PCIX_PS_REG(0x0084))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

681

#define D3_CRB_REG_FUN1 (UNM_PCIX_PS_REG(0x1084))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

682

#define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

683

#define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

686

#define ISR_I2Q_CLR_PCI_LO (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_LO))

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h

687

#define ISR_I2Q_CLR_PCI_HI (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_HI))