UNM_NIC_REG
#define CRB_SW_INT_MASK_0 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0)
#define CRB_SW_INT_MASK_1 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1)
#define CRB_SW_INT_MASK_2 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2)
#define CRB_SW_INT_MASK_3 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3)
#define CRB_SW_INT_MASK_4 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4)
#define CRB_SW_INT_MASK_5 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5)
#define CRB_SW_INT_MASK_6 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6)
#define CRB_SW_INT_MASK_7 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7)
#define CRB_NIC_DEBUG_STRUCT_BASE UNM_NIC_REG(0x288)
#define CRB_NIC_CAPABILITIES_HOST UNM_NIC_REG(0x1a8)
#define CRB_NIC_MSI_MODE_HOST UNM_NIC_REG(0x270)
#define CRB_EPG_QUEUE_BUSY_COUNT UNM_NIC_REG(0x200)
#define CRB_V2P_0 UNM_NIC_REG(0x290)
#define CRB_V2P_1 UNM_NIC_REG(0x294)
#define CRB_V2P_2 UNM_NIC_REG(0x298)
#define CRB_V2P_3 UNM_NIC_REG(0x29c)
#define CRB_DRIVER_VERSION UNM_NIC_REG(0x2a0)
#define CRB_CNT_DBG1 UNM_NIC_REG(0x2a4)
#define CRB_CNT_DBG2 UNM_NIC_REG(0x2a8)
#define CRB_CNT_DBG3 UNM_NIC_REG(0x2ac)
#define CRB_CMD_PRODUCER_OFFSET UNM_NIC_REG(0x08)
#define CRB_CMD_CONSUMER_OFFSET UNM_NIC_REG(0x0c)
#define CRB_PAUSE_ADDR_LO UNM_NIC_REG(0x10)
#define CRB_PAUSE_ADDR_HI UNM_NIC_REG(0x14)
#define NX_CDRP_CRB_OFFSET UNM_NIC_REG(0x18)
#define NX_ARG1_CRB_OFFSET UNM_NIC_REG(0x1c)
#define NX_ARG2_CRB_OFFSET UNM_NIC_REG(0x20)
#define NX_ARG3_CRB_OFFSET UNM_NIC_REG(0x24)
#define NX_SIGN_CRB_OFFSET UNM_NIC_REG(0x28)
#define CRB_CMDPEG_CMDRING UNM_NIC_REG(0x38)
#define CRB_HOST_DUMMY_BUF_ADDR_HI UNM_NIC_REG(0x3c)
#define CRB_HOST_DUMMY_BUF_ADDR_LO UNM_NIC_REG(0x40)
#define CRB_CMDPEG_STATE UNM_NIC_REG(0x50)
#define CRB_GLOBAL_INT_COAL UNM_NIC_REG(0x64)
#define CRB_INT_COAL_MODE UNM_NIC_REG(0x68)
#define CRB_MAX_RCV_BUFS UNM_NIC_REG(0x6c)
#define CRB_TX_INT_THRESHOLD UNM_NIC_REG(0x70)
#define CRB_RX_PKT_TIMER UNM_NIC_REG(0x74)
#define CRB_TX_PKT_TIMER UNM_NIC_REG(0x78)
#define CRB_RX_PKT_CNT UNM_NIC_REG(0x7c)
#define CRB_RX_TMR_CNT UNM_NIC_REG(0x80)
#define CRB_RCV_INTR_COUNT UNM_NIC_REG(0x84)
#define CRB_XG_STATE UNM_NIC_REG(0x94)
#define CRB_XG_STATE_P3 UNM_NIC_REG(0x98)
#define CRB_TX_STATE UNM_NIC_REG(0xac)
#define CRB_TX_COUNT UNM_NIC_REG(0xb0)
#define CRB_RX_STATE UNM_NIC_REG(0xb4)
#define CRB_RX_PERF_DEBUG_1 UNM_NIC_REG(0xb8)
#define CRB_RX_LRO_CONTROL UNM_NIC_REG(0xbc)
#define CRB_MPORT_MODE UNM_NIC_REG(0xc4)
#define CRB_INT_VECTOR UNM_NIC_REG(0xd4)
#define CRB_PF_LINK_SPEED_1 UNM_NIC_REG(0xe8)
#define CRB_PF_LINK_SPEED_2 UNM_NIC_REG(0xec)
#define CRB_HOST_DUMMY_BUF UNM_NIC_REG(0xfc)
#define CRB_SCRATCHPAD_TEST UNM_NIC_REG(0x280)
#define CRB_RCVPEG_STATE UNM_NIC_REG(0x13c)
#define CRB_CMD_PRODUCER_OFFSET_1 UNM_NIC_REG(0x1ac)
#define CRB_CMD_CONSUMER_OFFSET_1 UNM_NIC_REG(0x1b0)
#define CRB_TEMP_STATE UNM_NIC_REG(0x1b4)
#define CRB_CMD_PRODUCER_OFFSET_2 UNM_NIC_REG(0x1b8)
#define CRB_CMD_CONSUMER_OFFSET_2 UNM_NIC_REG(0x1bc)
#define CRB_CMD_PRODUCER_OFFSET_3 UNM_NIC_REG(0x1d0)
#define CRB_CMD_CONSUMER_OFFSET_3 UNM_NIC_REG(0x1d4)
rcv_desc->host_rx_producer = UNM_NIC_REG(reg - 0x200);
recv_ctx->host_sds_consumer = UNM_NIC_REG(reg - 0x200);
adapter->interrupt_crb = UNM_NIC_REG(reg - 0x200);
UNM_NIC_REG(temp - 0x200);
{UNM_NIC_REG(0x188), UNM_NIC_REG(0x18c), UNM_NIC_REG(0x1c0)},
{UNM_NIC_REG(0x190), UNM_NIC_REG(0x194), UNM_NIC_REG(0x1c4)},
{UNM_NIC_REG(0x198), UNM_NIC_REG(0x19c), UNM_NIC_REG(0x1c8)},
{UNM_NIC_REG(0x1a0), UNM_NIC_REG(0x1a4), UNM_NIC_REG(0x1cc)}
UNM_NIC_REG(0x100),
UNM_NIC_REG(0x110),
UNM_NIC_REG(0x120)
UNM_NIC_REG(0x138),
UNM_NIC_REG(0x144),
UNM_NIC_REG(0x154),
UNM_NIC_REG(0x164)
UNM_NIC_REG(0x17c),
UNM_NIC_REG(0x1d8),
UNM_NIC_REG(0x1f8),
UNM_NIC_REG(0x208)
UNM_NIC_REG(0x220),
UNM_NIC_REG(0x22c),
UNM_NIC_REG(0x23c),
UNM_NIC_REG(0x24c)
UNM_NIC_REG(0x264),
#define CRB_CMD_PRODUCER_OFFSET (UNM_NIC_REG(0x08))
#define CRB_CMD_CONSUMER_OFFSET (UNM_NIC_REG(0x0c))
#define CRB_PAUSE_ADDR_LO (UNM_NIC_REG(0x10)) /* C0 EPG BUG */
#define CRB_PAUSE_ADDR_HI (UNM_NIC_REG(0x14))
#define NX_CDRP_CRB_OFFSET (UNM_NIC_REG(0x18))
#define NX_ARG1_CRB_OFFSET (UNM_NIC_REG(0x1c))
#define NX_ARG2_CRB_OFFSET (UNM_NIC_REG(0x20))
#define NX_ARG3_CRB_OFFSET (UNM_NIC_REG(0x24))
#define NX_SIGN_CRB_OFFSET (UNM_NIC_REG(0x28))
#define CRB_CMDPEG_CMDRING (UNM_NIC_REG(0x38))
#define CRB_HOST_DUMMY_BUF_ADDR_HI (UNM_NIC_REG(0x3c))
#define CRB_HOST_DUMMY_BUF_ADDR_LO (UNM_NIC_REG(0x40))
#define CRB_CMDPEG_STATE (UNM_NIC_REG(0x50))
#define BOOT_LOADER_DIMM_STATUS (UNM_NIC_REG(0x54))
#define CRB_GLOBAL_INT_COAL (UNM_NIC_REG(0x64)) /* intrt coalescing */
#define CRB_INT_COAL_MODE (UNM_NIC_REG(0x68))
#define CRB_MAX_RCV_BUFS (UNM_NIC_REG(0x6c))
#define CRB_TX_INT_THRESHOLD (UNM_NIC_REG(0x70))
#define CRB_RX_PKT_TIMER (UNM_NIC_REG(0x74))
#define CRB_TX_PKT_TIMER (UNM_NIC_REG(0x78))
#define CRB_RX_PKT_CNT (UNM_NIC_REG(0x7c))
#define CRB_RX_TMR_CNT (UNM_NIC_REG(0x80))
#define CRB_RCV_INTR_COUNT (UNM_NIC_REG(0x84))
#define CRB_XG_STATE (UNM_NIC_REG(0x94)) /* XG Link status */
#define CRB_XG_STATE_P3 (UNM_NIC_REG(0x98)) /* XG PF Link status */
#define CRB_TX_STATE (UNM_NIC_REG(0xac)) /* Debug -performance */
#define CRB_TX_COUNT (UNM_NIC_REG(0xb0))
#define CRB_RX_STATE (UNM_NIC_REG(0xb4))
#define CRB_RX_PERF_DEBUG_1 (UNM_NIC_REG(0xb8))
#define CRB_RX_LRO_CONTROL (UNM_NIC_REG(0xbc)) /* LRO On/OFF */
#define CRB_MPORT_MODE (UNM_NIC_REG(0xc4)) /* Multiport Mode */
#define CRB_DMA_SHIFT (UNM_NIC_REG(0xcc)) /* DMA mask extension */
#define CRB_INT_VECTOR (UNM_NIC_REG(0xd4))
#define CRB_PF_LINK_SPEED_1 (UNM_NIC_REG(0xe8))
#define CRB_PF_LINK_SPEED_2 (UNM_NIC_REG(0xec))
#define CRB_PF_MAX_LINK_SPEED_1 (UNM_NIC_REG(0xf0))
#define CRB_PF_MAX_LINK_SPEED_2 (UNM_NIC_REG(0xf4))
#define CRB_HOST_DUMMY_BUF (UNM_NIC_REG(0xfc))
#define CRB_SCRATCHPAD_TEST (UNM_NIC_REG(0x280))
#define CRB_RCVPEG_STATE (UNM_NIC_REG(0x13c))
#define CRB_CMD_PRODUCER_OFFSET_1 (UNM_NIC_REG(0x1ac))
#define CRB_CMD_CONSUMER_OFFSET_1 (UNM_NIC_REG(0x1b0))
#define CRB_TEMP_STATE (UNM_NIC_REG(0x1b4))
#define CRB_CMD_PRODUCER_OFFSET_2 (UNM_NIC_REG(0x1b8))
#define CRB_CMD_CONSUMER_OFFSET_2 (UNM_NIC_REG(0x1bc))
#define CRB_CMD_PRODUCER_OFFSET_3 (UNM_NIC_REG(0x1d0))
#define CRB_CMD_CONSUMER_OFFSET_3 (UNM_NIC_REG(0x1d4))
#define CRB_SW_INT_MASK_0 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0))
#define CRB_SW_INT_MASK_1 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1))
#define CRB_SW_INT_MASK_2 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2))
#define CRB_SW_INT_MASK_3 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3))
#define CRB_SW_INT_MASK_4 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4))
#define CRB_SW_INT_MASK_5 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5))
#define CRB_SW_INT_MASK_6 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6))
#define CRB_SW_INT_MASK_7 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7))
#define CRB_NIC_DEBUG_STRUCT_BASE (UNM_NIC_REG(0x288))
#define CRB_NIC_CAPABILITIES_HOST (UNM_NIC_REG(0x1a8))
#define CRB_NIC_CAPABILITIES_FW (UNM_NIC_REG(0x1dc))
#define CRB_NIC_MSI_MODE_HOST (UNM_NIC_REG(0x270))
#define CRB_NIC_MSI_MODE_FW (UNM_NIC_REG(0x274))
#define CRB_EPG_QUEUE_BUSY_COUNT (UNM_NIC_REG(0x200))
#define CRB_V2P_0 (UNM_NIC_REG(0x290))
#define CRB_V2P_1 (UNM_NIC_REG(0x294))
#define CRB_V2P_2 (UNM_NIC_REG(0x298))
#define CRB_V2P_3 (UNM_NIC_REG(0x29c))
#define CRB_DRIVER_VERSION (UNM_NIC_REG(0x2a0))
#define CRB_CNT_DBG1 (UNM_NIC_REG(0x2a4))
#define CRB_CNT_DBG2 (UNM_NIC_REG(0x2a8))
#define CRB_CNT_DBG3 (UNM_NIC_REG(0x2ac))