UNM_CRB_I2Q
ql_8021_wr_32(ha, UNM_CRB_I2Q + 0x10, 0);
ql_8021_wr_32(ha, UNM_CRB_I2Q + 0x14, 0);
ql_8021_wr_32(ha, UNM_CRB_I2Q + 0x18, 0);
ql_8021_wr_32(ha, UNM_CRB_I2Q + 0x1c, 0);
ql_8021_wr_32(ha, UNM_CRB_I2Q + 0x20, 0);
ql_8021_wr_32(ha, UNM_CRB_I2Q + 0x24, 0);
#define UNM_I2Q_CONFIG (UNM_CRB_I2Q + 0x00000)
#define UNM_I2Q_ENA_PCI_LO (UNM_CRB_I2Q + 0x00010)
#define UNM_I2Q_ENA_PCI_HI (UNM_CRB_I2Q + 0x00014)
#define UNM_I2Q_ENA_CASPER_LO (UNM_CRB_I2Q + 0x00018)
#define UNM_I2Q_ENA_CASPER_HI (UNM_CRB_I2Q + 0x0001c)
#define UNM_I2Q_ENA_QM_LO (UNM_CRB_I2Q + 0x00020)
#define UNM_I2Q_ENA_QM_HI (UNM_CRB_I2Q + 0x00024)
#define UNM_I2Q_CLR_PCI_LO (UNM_CRB_I2Q + 0x00030)
#define UNM_I2Q_CLR_PCI_HI (UNM_CRB_I2Q + 0x00034)
#define UNM_I2Q_CLR_CASPER_LO (UNM_CRB_I2Q + 0x00038)
#define UNM_I2Q_CLR_CASPER_HI (UNM_CRB_I2Q + 0x0003c)
#define UNM_I2Q_MSG_HDR_LO(I) (UNM_CRB_I2Q + 0x00100 + (I)*0x8)
#define UNM_I2Q_MSG_HDR_HI(I) (UNM_CRB_I2Q + 0x00104 + (I)*0x8)
#define UNM_I2Q_CONFIG (UNM_CRB_I2Q + 0x00000)
#define UNM_I2Q_ENA_PCI_LO (UNM_CRB_I2Q + 0x00010)
#define UNM_I2Q_ENA_PCI_HI (UNM_CRB_I2Q + 0x00014)
#define UNM_I2Q_ENA_CASPER_LO (UNM_CRB_I2Q + 0x00018)
#define UNM_I2Q_ENA_CASPER_HI (UNM_CRB_I2Q + 0x0001c)
#define UNM_I2Q_ENA_QM_LO (UNM_CRB_I2Q + 0x00020)
#define UNM_I2Q_ENA_QM_HI (UNM_CRB_I2Q + 0x00024)
#define UNM_I2Q_CLR_PCI_LO (UNM_CRB_I2Q + 0x00030)
#define UNM_I2Q_CLR_PCI_HI (UNM_CRB_I2Q + 0x00034)
#define UNM_I2Q_CLR_CASPER_LO (UNM_CRB_I2Q + 0x00038)
#define UNM_I2Q_CLR_CASPER_HI (UNM_CRB_I2Q + 0x0003c)
#define UNM_I2Q_MSG_HDR_LO(I) (UNM_CRB_I2Q + 0x00100 + (I) * 0x8)
#define UNM_I2Q_MSG_HDR_HI(I) (UNM_CRB_I2Q + 0x00104 + (I) * 0x8)