UNM_CRB_DDR_NET
if ((off & 0x0ff00000) == UNM_CRB_DDR_NET) {
mem_crb = UNM_CRB_DDR_NET;
mem_crb = UNM_CRB_DDR_NET;
#define UNM_MIU_MN_CONTROL (UNM_CRB_DDR_NET + MIU_CONTROL)
#define UNM_MIU_MN_TAG (UNM_CRB_DDR_NET + MIU_TAG)
#define UNM_MIU_MN_TEST_AGT_ADDR_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_LO)
#define UNM_MIU_MN_TEST_AGT_ADDR_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_HI)
#define UNM_MIU_MN_TEST_AGT_WRDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_LO)
#define UNM_MIU_MN_TEST_AGT_WRDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_HI)
#define UNM_MIU_MN_TEST_AGT_CTRL (UNM_CRB_DDR_NET + MIU_TEST_AGT_CTRL)
#define UNM_MIU_MN_TEST_AGT_RDDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_LO)
#define UNM_MIU_MN_TEST_AGT_RDDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_HI)
mem_crb = (uptr_t)(pci_base_offset(adapter, UNM_CRB_DDR_NET));
mem_crb = (uptr_t)(pci_base_offset(adapter, UNM_CRB_DDR_NET));
mem_crb = UNM_CRB_DDR_NET;
mem_crb = UNM_CRB_DDR_NET;