usr/src/uts/intel/io/amdzen/zen_umc.c

2781

UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

2783

UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

2785

UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

2797

UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

2799

UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

2801

UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

3023

cs->ucs_rm_bits[3] = UMC_RMSEL_DDR5_GET_RM3(val) + UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

3024

cs->ucs_rm_bits[2] = UMC_RMSEL_DDR5_GET_RM2(val) + UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

3025

cs->ucs_rm_bits[1] = UMC_RMSEL_DDR5_GET_RM1(val) + UMC_RMSEL_BASE;

usr/src/uts/intel/io/amdzen/zen_umc.c

3026

cs->ucs_rm_bits[0] = UMC_RMSEL_DDR5_GET_RM0(val) + UMC_RMSEL_BASE;