TXC_FZC_CNTL_REG_READ64
TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val);
TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val);
TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val)
TXC_FZC_CNTL_REG_READ64(handle, TXC_PKT_STUFFED_REG, port, &value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_PKT_XMIT_REG, port, &value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_ROECC_ST_REG, port, &ecc.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA0_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA1_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA2_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA3_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA4_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_CTL_REG, port, &ctl.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE0_REG, port, &s0.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE1_REG, port, &s1.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE2_REG, port, &s2.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE3_REG, port, &s3.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_TIDS_REG, port, &tids.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_SFECC_ST_REG, port, &ecc.value);
TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA0_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA1_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA2_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA3_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA4_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port,
TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port,