STAT
if (STAT(Gen.g_dirfd,
if (STAT(Gen.g_dirfd, Gen.g_nam_p, &SrcSt) == -1) {
X(STAT, "stat"),
STAT->cs_real_statefsz += cpr_buf_size;
STAT->cs_nocomp_statefsz = sizeof (cdd_t) + sizeof (cmd_t) +
(STAT->cs_nocomp_statefsz > STAT->cs_est_statefsz)) {
cpr_term.real_statef_size = STAT->cs_real_statefsz +
STAT->cs_real_statefsz);
STAT->cs_upage2statef = dcnt;
STAT->cs_dumped_statefsz += mmu_ptob(npg);
STAT->cs_nosw_pages = k_anoninfo.ani_mem_resv;
if (STAT->cs_nosw_pages < 0)
STAT->cs_nosw_pages = 0;
nback = mmu_ptob(STAT->cs_nosw_pages);
STAT->cs_est_statefsz = size;
STAT->cs_est_statefsz = size;
struct cpr_stat *cp = STAT;
STAT->cs_real_statefsz = 0;
STAT->cs_dumped_statefsz = 0;
STAT->cs_real_statefsz = cpr_term.real_statef_size;
STAT->cs_nocomp_statefsz*100)/
STAT->cs_real_statefsz);
if (STAT->cs_min_comprate == 0 ||
(STAT->cs_min_comprate > cur_comprate))
STAT->cs_min_comprate = cur_comprate;
struct cpr_stat *cp = STAT;
struct cpr_stat *cp = STAT;
struct cpr_stat *cp = STAT;
#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
v4->tcp_out_rsts = STAT(OUT_RST);
v6->tcp_out_rsts = STAT(OUT_RST);
STAT(Px, 0_9V_ADC), /* 0x20 IN_0V9_ADC */
STAT(Px, INT_TEMP2), /* 0x21 CONTROLLER_2_TEMP */
STAT(Px, VREG_TEMP), /* 0x22 VREG_INTERNAL_TEMP */
STAT(Px, VREG_0_9V_TEMP), /* 0x23 VREG_0V9_TEMP */
STAT(Px, VREG_1_2V_TEMP), /* 0x24 VREG_1V2_TEMP */
STAT(Px, INT_VPTAT), /* 0x25 CTRLR. VPTAT */
STAT(Px, INT_ADC_TEMP), /* 0x26 CTRLR. INTERNAL_TEMP */
STAT(Px, EXT_VPTAT), /* 0x27 CTRLR. VPTAT_EXTADC */
STAT(Px, EXT_ADC_TEMP), /* 0x28 CTRLR. INTERNAL_TEMP_EXTADC */
STAT(Px, AMBIENT_TEMP), /* 0x29 AMBIENT_TEMP */
STAT(Px, AIRFLOW), /* 0x2a AIRFLOW */
STAT(Px, VDD08D_VSS08D_CSR), /* 0x2b VDD08D_VSS08D_CSR */
STAT(Px, VDD08D_VSS08D_CSR_EXTADC), /* 0x2c VDD08D_VSS08D_CSR_EXTADC */
STAT(Px, HOTPOINT_TEMP), /* 0x2d HOTPOINT_TEMP */
STAT(P1, PHY_POWER_SWITCH_PORT0), /* 0x2e PHY_POWER_SWITCH_PORT0 */
STAT(P2, PHY_POWER_SWITCH_PORT1), /* 0x2f PHY_POWER_SWITCH_PORT1 */
STAT(Px, MUM_VCC), /* 0x30 MUM_VCC */
STAT(Px, 0V9_A), /* 0x31 0V9_A */
STAT(Px, I0V9_A), /* 0x32 I0V9_A */
STAT(Px, 0V9_A_TEMP), /* 0x33 0V9_A_TEMP */
STAT(Px, 0V9_B), /* 0x34 0V9_B */
STAT(Px, I0V9_B), /* 0x35 I0V9_B */
STAT(Px, 0V9_B_TEMP), /* 0x36 0V9_B_TEMP */
STAT(Px, CCOM_AVREG_1V2_SUPPLY), /* 0x37 CCOM_AVREG_1V2_SUPPLY */
STAT(Px, CCOM_AVREG_1V2_SUPPLY_EXT_ADC),
STAT(Px, CCOM_AVREG_1V8_SUPPLY), /* 0x39 CCOM_AVREG_1V8_SUPPLY */
STAT(Px, CCOM_AVREG_1V8_SUPPLY_EXT_ADC),
STAT(Px, CONTROLLER_MASTER_VPTAT), /* 0x40 MASTER_VPTAT */
STAT(Px, CONTROLLER_MASTER_INTERNAL_TEMP), /* 0x41 MASTER_INT_TEMP */
STAT(Px, CONTROLLER_MASTER_VPTAT_EXT_ADC), /* 0x42 MAST_VPTAT_EXT_ADC */
STAT(Px, CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC),
STAT(Px, CONTROLLER_SLAVE_VPTAT), /* 0x44 SLAVE_VPTAT */
STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP), /* 0x45 SLAVE_INTERNAL_TEMP */
STAT(Px, CONTROLLER_SLAVE_VPTAT_EXT_ADC), /* 0x46 SLAVE_VPTAT_EXT_ADC */
STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC),
STAT(Px, SODIMM_VOUT), /* 0x49 SODIMM_VOUT */
STAT(Px, SODIMM_0_TEMP), /* 0x4a SODIMM_0_TEMP */
STAT(Px, SODIMM_1_TEMP), /* 0x4b SODIMM_1_TEMP */
STAT(Px, PHY0_VCC), /* 0x4c PHY0_VCC */
STAT(Px, PHY1_VCC), /* 0x4d PHY1_VCC */
STAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */
STAT(Px, BOARD_FRONT_TEMP), /* 0x4f BOARD_FRONT_TEMP */
STAT(Px, BOARD_BACK_TEMP), /* 0x50 BOARD_BACK_TEMP */
STAT(Px, INT_TEMP), /* 0x00 CONTROLLER_TEMP */
STAT(Px, EXT_TEMP), /* 0x01 PHY_COMMON_TEMP */
STAT(Px, INT_COOLING), /* 0x02 CONTROLLER_COOLING */
STAT(P1, EXT_TEMP), /* 0x03 PHY0_TEMP */
STAT(P1, EXT_COOLING), /* 0x04 PHY0_COOLING */
STAT(P2, EXT_TEMP), /* 0x05 PHY1_TEMP */
STAT(P2, EXT_COOLING), /* 0x06 PHY1_COOLING */
STAT(Px, 1V), /* 0x07 IN_1V0 */
STAT(Px, 1_2V), /* 0x08 IN_1V2 */
STAT(Px, 1_8V), /* 0x09 IN_1V8 */
STAT(Px, 2_5V), /* 0x0a IN_2V5 */
STAT(Px, 3_3V), /* 0x0b IN_3V3 */
STAT(Px, 12V), /* 0x0c IN_12V0 */
STAT(Px, 1_2VA), /* 0x0d IN_1V2A */
STAT(Px, VREF), /* 0x0e IN_VREF */
STAT(Px, VAOE), /* 0x0f OUT_VAOE */
STAT(Px, AOE_TEMP), /* 0x10 AOE_TEMP */
STAT(Px, PSU_AOE_TEMP), /* 0x11 PSU_AOE_TEMP */
STAT(Px, PSU_TEMP), /* 0x12 PSU_TEMP */
STAT(Px, FAN0), /* 0x13 FAN_0 */
STAT(Px, FAN1), /* 0x14 FAN_1 */
STAT(Px, FAN2), /* 0x15 FAN_2 */
STAT(Px, FAN3), /* 0x16 FAN_3 */
STAT(Px, FAN4), /* 0x17 FAN_4 */
STAT(Px, VAOE_IN), /* 0x18 IN_VAOE */
STAT(Px, IAOE), /* 0x19 OUT_IAOE */
STAT(Px, IAOE_IN), /* 0x1a IN_IAOE */
STAT(Px, NIC_POWER), /* 0x1b NIC_POWER */
STAT(Px, 0_9V), /* 0x1c IN_0V9 */
STAT(Px, I0_9V), /* 0x1d IN_I0V9 */
STAT(Px, I1_2V), /* 0x1e IN_I1V2 */
#define HCI1394_INIT_IT_OLAST(DESCP, STAT, INTR, REQCOUNT) ((DESCP)->hdr = 0 |\
(DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_REF | (INTR) | \
#define HCI1394_INIT_IT_OLAST_IMM(DESCP, STAT, INTR) ((DESCP)->hdr = 0 | \
(DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_IMMED | (INTR) | \
#define HCI1394_INIT_IR_PPB_ILAST(DESCP, STAT, INTR, WAIT, REQCOUNT) \
(DESCP)->hdr = 0 | (DESC_TY_INPUT_LAST | (STAT) | DESC_KEY_REF | \
STAT->cs_dumped_statefsz += mmu_ptob(dirty_npages);