SOCKET_BUS
#define MC_COR_ECC_CNT(chipid, reg) (*pci_getl_func)(SOCKET_BUS(chipid), \
#define CPU_ID_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 0, 0, 0, 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x48, 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x4c, 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x50, 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0, 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x4c, 0)
#define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \
#define MC_SSR_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x48, 0)
#define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \
#define MC_SSR_SCRUB_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, \
#define MC_RAS_ENABLES_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x50, 0)
#define MC_RAS_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x54, 0)
#define MC_SSR_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x60, 0)
#define MC_CHANNEL_MAPPER_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, \
nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x80 + ((select) * 4), 0)
nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0)
nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0)
nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0)
nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0)
nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0)
nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x58, 0)
nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0x80 + (4 * (rule)), 0)
nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0xc0 + (4 * (rule)), 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0x80 + (4 * (rule)), 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0xc0 + (4 * (rule)), 0)
nhm_pci_getl(SOCKET_BUS(cpu), 3, 4, 0x50, 0)
slot = SOCKET_BUS(0) - bus;
SOCKET_BUS(i), j, k, 0);
if (bus >= SOCKET_BUS(MAX_CPU_NODES) && bus <= SOCKET_BUS(0) &&