usr/src/uts/intel/pcbe/p4_pcbe.c

217

{ 0, 0x3B2, BPU0_map }, /* 0 */

usr/src/uts/intel/pcbe/p4_pcbe.c

219

{ 1, 0x3B4, BPU0_map }, /* 1 */

usr/src/uts/intel/pcbe/p4_pcbe.c

221

{ 2, 0x3AA, BPU0_map }, /* 2 */

usr/src/uts/intel/pcbe/p4_pcbe.c

223

{ 3, 0x3B6, BPU0_map }, /* 3 */

usr/src/uts/intel/pcbe/p4_pcbe.c

225

{ 4, 0x3AC, BPU0_map }, /* 4 */

usr/src/uts/intel/pcbe/p4_pcbe.c

227

{ 5, 0x3C8, BPU0_map }, /* 5 */

usr/src/uts/intel/pcbe/p4_pcbe.c

229

{ 6, 0x3A2, BPU0_map }, /* 6 */

usr/src/uts/intel/pcbe/p4_pcbe.c

231

{ 7, 0x3A0, BPU0_map }, /* 7 */