SET8
SET8(dev, REG_MISC2, MISC2_CHB3D8C);
SET8(dev, REG_MIX2, MIX2_WSMUTE);
SET8(dev, REG_MIX3, MIX3_RAUXREN | MIX3_RAUXLEN);
SET8(dev, REG_MIX3, MIX3_VAUXRM | MIX3_VAUXLM);
SET8(dev, REG_MIX2, MIX2_WAVEIN_L | MIX2_WAVEIN_R);
SET8(dev, REG_MIX3, MIX3_MICGAINZ);
SET8(dev, CONC_bSERCTL_OFF, CONC_SERCTL_DAC1IE);
SET8(dev, CONC_bSERCTL_OFF, CONC_SERCTL_ADCIE);
SET8(dev, CONC_bSERCTL_OFF, CONC_SERCTL_DAC2IE);
SET8(dev, CONC_bSERFMT_OFF,
SET8(dev, CONC_bDEVCTL_OFF,
SET8(dev, CONC_bSERCTL_OFF, CONC_SERCTL_DAC1IE);
SET8(dev, CONC_bDEVCTL_OFF, CONC_DEVCTL_ADC_EN);
SET8(dev, CONC_bSERCTL_OFF, CONC_SERCTL_ADCIE);
SET8(dev, CONC_bMISCCTL_OFF, CONC_MISCCTL_SYN_44KHZ);
SET8(dev, CONC_bDEVCTL_OFF, CONC_DEVCTL_DAC_EN);
SET8(dev, CONC_bDEVCTL_OFF, CONC_DEVCTL_SYN_EN);
SET8(dev, CONC_bDEVCTL_OFF, CONC_DEVCTL_ADC_EN);
SET8(dev, CONC_bMISCCTL_OFF, CONC_MISCCTL_SYN_44KHZ);
SET8(ss, REG_HOST_CONTROL, HOST_CONTROL_LED_ON);
SET8(ss, REG_HOST_CONTROL, HOST_CONTROL_DATA_WIDTH);
SET8(ss, REG_HOST_CONTROL, HOST_CONTROL_HIGH_SPEED_EN);
SET8(ss, REG_HOST_CONTROL, HOST_CONTROL_HIGH_SPEED_EN);