SCL_ALL
ASSERT(spa_config_held(spa, SCL_ALL, RW_READER) != 0);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_exit(spa, SCL_ALL, FTAG);
ASSERT(spa_config_held(os->os_spa, SCL_ALL, RW_WRITER) == 0 ||
ASSERT(spa_config_held(mc->mc_spa, SCL_ALL, RW_READER) ||
spa_config_held(mc->mc_spa, SCL_ALL, RW_WRITER));
ASSERT3U(spa_config_held(spa, SCL_ALL, RW_READER), !=, 0);
ASSERT3U(spa_config_held(spa, SCL_ALL, RW_READER), !=, 0);
ASSERT3U(spa_config_held(spa, SCL_ALL, RW_READER), !=, 0);
ASSERT3U(spa_config_held(spa, SCL_ALL, RW_READER), !=, 0);
ASSERT3U(spa_config_held(spa, SCL_ALL, RW_READER), !=, 0);
int locks = spa_config_held(spa, SCL_ALL, RW_WRITER);
spa_config_enter(spa, SCL_ALL, spa, RW_WRITER);
spa_config_exit(spa, SCL_ALL, spa);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_vdev_state_enter(spa, SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == 0);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == 0);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == 0);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
spa_config_enter(spa, SCL_ALL, spa, RW_WRITER);
spa_config_exit(spa, SCL_ALL, spa);
spa_config_enter(spa, SCL_ALL, spa, RW_WRITER);
spa_config_exit(spa, SCL_ALL, spa);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
ASSERT(spa_config_held(spa, SCL_ALL, RW_READER) != 0);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(cvd->vdev_spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_READER) != 0);
ASSERT0(spa_config_held(vd->vdev_spa, SCL_ALL, RW_WRITER));
ASSERT(spa_config_held(spa, SCL_ALL, RW_READER) != 0);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(pvd->vdev_spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(vd->vdev_spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_READER) != 0);
ASSERT(spa_config_held(spa, SCL_ALL, RW_READER) != 0);
ASSERT0(spa_config_held(vd->vdev_spa, SCL_ALL, RW_WRITER));
ASSERT0(spa_config_held(vd->vdev_spa, SCL_ALL, RW_WRITER));
ASSERT(!spa_config_held(vd->vdev_spa, SCL_ALL, RW_WRITER));
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
spa_config_enter(spa, SCL_ALL, FTAG, RW_WRITER);
spa_config_exit(spa, SCL_ALL, FTAG);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL);
ASSERT3U(spa_config_held(nzio->io_spa, SCL_ALL, RW_READER), !=, 0);
ASSERT(!spa_config_held(vd->vdev_spa, SCL_ALL, RW_WRITER));
spa_vdev_state_enter(spa, SCL_ALL);
spa_vdev_state_enter(spa, SCL_ALL);