BIT_ULL
#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
BIT_ULL(I40E_PHY_TYPE_XAUI) | \
BIT_ULL(I40E_PHY_TYPE_XFI) | \
BIT_ULL(I40E_PHY_TYPE_SFI) | \
BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
(u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
(u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
mask = BIT_ULL(ce_info->width) - 1;
obj->size = BIT_ULL(size_exp);
obj->size = BIT_ULL(size_exp);
obj->size = BIT_ULL(size_exp);
obj->size = BIT_ULL(size_exp);
mask = BIT_ULL(ce_info->width) - 1;
#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
#define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
#define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
#define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
#define I40E_HW_FLAG_DROP_MODE BIT_ULL(7)
#define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
#ifndef BIT_ULL
#define IXGBE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
#define IXGBE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
#define IXGBE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
#define IXGBE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
#define IXGBE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
#define IXGBE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
#define IXGBE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
#define IXGBE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
#define IXGBE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
#define IXGBE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
#define IXGBE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
#define IXGBE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
#define IXGBE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
#define IXGBE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
#define IXGBE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
#define IXGBE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
#define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
#define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
#define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
#define IXGBE_PHY_TYPE_HIGH_10BASE_T BIT_ULL(1)
#define IXGBE_PHY_TYPE_HIGH_10M_SGMII BIT_ULL(2)
#define IXGBE_PHY_TYPE_HIGH_2500M_SGMII BIT_ULL(56)
#define IXGBE_PHY_TYPE_HIGH_100M_USXGMII BIT_ULL(57)
#define IXGBE_PHY_TYPE_HIGH_1G_USXGMII BIT_ULL(58)
#define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII BIT_ULL(59)
#define IXGBE_PHY_TYPE_HIGH_5G_USXGMII BIT_ULL(60)
#define IXGBE_PHY_TYPE_HIGH_10G_USXGMII BIT_ULL(61)