BIT_8
#define PHY_AN_AD_1000BASET_HALF BIT_8
#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11)
#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10)
#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9)
#define BCM540X_DSP_FILTER_FFE BIT_8
#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8
#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9)
#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_AUX_10BASET_HD BIT_8
#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9)
#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10)
#define BCM540X_AUX_1000BASET_FD (BIT_8 | BIT_9 | BIT_10)
#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8
#define PHY_AN_AD_100BASETX_FULL BIT_8
#define PHY_AN_AD_1000X_ASYM_PAUSE BIT_8
#define PHY_LINK_PARTNER_100BASETX_FULL BIT_8
if ((REG_RD32(qlt, REG_RISC_STATUS) & BIT_8) == 0) {
(REG_RD32(qlt, REG_RISC_STATUS) & BIT_8) == 0;
mcp->to_fw_mask |= BIT_1 | BIT_8;
BIT_14 | BIT_8 | BIT_7 | BIT_4);
DMEM_WR32(qlt, icb+0x64, BIT_14 | BIT_8 | BIT_7 |
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
if (risc_status & BIT_8) {
if (risc_status & BIT_8) {
mcp->to_fw_mask |= BIT_9 | BIT_8;
BIT_11 | BIT_10 | BIT_9 | BIT_8 | \
#define RISC_PAUSED BIT_8
#define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11)
(hccr_reg & (BIT_15 | BIT_13 | BIT_11 | BIT_8))) {
if (pkt->log.io_param[0] & BIT_8) {
#define SKD_CONSTRUCTED BIT_8
#define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */
#define TQF_LOGIN_NEEDED BIT_8
#define QL_MINOR_NODE_CREATED BIT_8
#define MENLO_LOGIN_OPERATIONAL (uint64_t)BIT_8
#define MARKER_ACTIVE (uint64_t)BIT_8
#define CFG_CTRL_83XX (uint64_t)BIT_8
#define PRLI_W3_RETRY BIT_8
#define RH_RISC_PAUSED BIT_8 /* RISC Paused bit. */
#define CFO_CLASS_2 BIT_8
#define IDC_TIMEOUT_MASK (BIT_11 | BIT_10 | BIT_9 | BIT_8)
#define GID_FP_IN_ORDER BIT_8
#define MBX_8 BIT_8
#define IMO_QOS_BANDWIDTH_MODE BIT_8
#define INIT_ADD_INTERRUPT BIT_8
#define CFG_CKSUM_FULL_IPv6 BIT_8
#define ADAPTER_SUSPENDED BIT_8
#define CSR_RR BIT_8
#define RT_IDX_CAM_BIT0 BIT_8
#define CQ_8_NOT_EMPTY BIT_8
#define RISC_RESET BIT_8