BIT_6
#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6
#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)
#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6
#define PHY_AN_AD_10BASET_FULL BIT_6
#define PHY_AN_AD_1000X_HALF_DUPLEX BIT_6
#define PHY_LINK_PARTNER_10BASET_FULL BIT_6
} else if (tm & BIT_6) {
(qlt->qlt_mq_enabled))) && (qlt->fw_attr & BIT_6)) {
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
mcp->to_fw[1] = BIT_6 | BIT_1;
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
mcp->to_fw[1] = BIT_6;
mcp->from_fw_mask = BIT_11 | BIT_10 | BIT_6 | BIT_3 | BIT_2 |
mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7;
mcp->to_fw_mask |= BIT_2 | BIT_3 | BIT_7 | BIT_6;
flags = (uint16_t)(BIT_6 | BIT_15 |
flags = (uint16_t)(flags | BIT_6);
req1f = BIT_6;
flags = (uint16_t)(flags | BIT_6);
else if (tm & BIT_6)
ASSERT((flags & (BIT_6 | BIT_7)) == BIT_7);
BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
#define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
#define H2RISC_INTR BIT_6
} else if (tm & BIT_6) {
*bptr & (BIT_6 | BIT_5 | BIT_4))) {
(*bptr & ~(BIT_6|BIT_5|BIT_4));
(echo.options | BIT_6);
nv->firmware_options_3[1] = BIT_6;
BIT_6);
(icb->firmware_options_2[3] | BIT_6 | BIT_5);
(icb->firmware_options_2[3] | ~(BIT_6 | BIT_5));
~(BIT_6 | BIT_5 | BIT_4));
~(BIT_6 | BIT_5 | BIT_4));
(icb->firmware_options_2[2] & ~(BIT_6 | BIT_5));
(icb->firmware_options_2[2] | BIT_7 | BIT_6);
(icb->firmware_options_2[2] | BIT_6);
(icb->firmware_options[0] | BIT_6 | BIT_1);
BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0);
(icb->firmware_options[1] | BIT_7 | BIT_6);
pkt->control_flags_l = BIT_6;
nv->firmware_options_3[1] = BIT_6;
if (pkt->entry_status & BIT_6) {
port_no = (uint8_t)(port_no | BIT_6);
mcp->mb[1] = BIT_6;
if (echo_pt->options & BIT_6) {
#define SKD_REGS_MAPPED BIT_6
#define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */
#define TQF_PLOGI_PROGRS BIT_6
#define QL_TASK_DAEMON_STARTED BIT_6
#define IP_ENABLED (uint64_t)BIT_6
#define NEED_UNSOLICITED_BUFFERS (uint64_t)BIT_6
#define CFG_LR_SUPPORT (uint64_t)BIT_6
#define PRLI_W3_DATA_OVERLAY_ALLOWED BIT_6
#define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6
#define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */
#define VPO_ENABLE_SNS_LOGIN_SCR BIT_6
#define SF_DATA_OUT BIT_6
#define CFO_EXPLICIT_LOGO BIT_6
#define CF_DATA_OUT BIT_6
#define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4)
#define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4)
#define MBC_LOOPBACK_64BIT BIT_6 /* 2200 0r 2300 */
#define MBC_ECHO_64BIT BIT_6 /* 64bit DMA address used */
#define MBX_6 BIT_6
#define FO1_DISABLE_GPIO BIT_6
#define FO1_DISABLE_LEDS BIT_6
#define FWATTRIB2_MQUE BIT_6
#define IMO_INTERRUPT_HANDSHAKE BIT_6
#define LINK_CONFIG_PAUSE_MASK (BIT_6 | BIT_5)
#define FLASH8192 BIT_6
#define LED_GREEN BIT_6
#define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6
#define INIT_MEMORY_ALLOC BIT_6
#define CFG_CKSUM_PARTIAL BIT_6
#define FLASH8192 BIT_6
#define RT_IDX_ETH_FCOE BIT_6
#define CQ_6_NOT_EMPTY BIT_6