BIT_5
#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5
#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
#define PHY_AN_AD_10BASET_HALF BIT_5
#define PHY_AN_AD_1000X_FULL_DUPLEX BIT_5
#define PHY_LINK_PARTNER_10BASET_HALF BIT_5
} else if (tm & BIT_5) {
DMEM_WR32(qlt, icb+0x5c, BIT_5 | BIT_4);
BIT_11 | BIT_5 | BIT_4 | BIT_2 | BIT_1 | BIT_0);
BIT_26 | BIT_23 | BIT_22 | BIT_5);
icb+0x60, BIT_26 | BIT_23 | BIT_22 | BIT_5);
DMEM_WR32(qlt, icb+0x5c, BIT_11 | BIT_5 | BIT_4 |
DMEM_WR32(qlt, icb+0x60, BIT_5);
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
req1f = BIT_5;
else if (tm & BIT_5)
BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
#define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
#define RISC_RESET BIT_5
#define PCI_X_XFER_CTRL (BIT_4 | BIT_5)
} else if (tm & BIT_5) {
(FCOE_B2V_4(src + offset) & BIT_5) ? 1 : 0;
if (flash_data & BIT_5 && cnt > 2) {
*bptr & (BIT_6 | BIT_5 | BIT_4))) {
(*bptr & ~(BIT_6|BIT_5|BIT_4));
nv->firmware_options_1[1] = BIT_5;
nv->firmware_options_2[0] = BIT_5;
(icb->firmware_options_1[1] | BIT_5 | BIT_2);
~(BIT_5 | BIT_4));
(icb->firmware_options_2[3] | BIT_6 | BIT_5);
(icb->firmware_options_2[3] | ~(BIT_6 | BIT_5));
~(BIT_6 | BIT_5 | BIT_4));
~(BIT_6 | BIT_5 | BIT_4));
(icb->firmware_options_2[2] & ~(BIT_6 | BIT_5));
(icb->firmware_options_2[2] & ~BIT_5);
(icb->firmware_options_2[2] & ~(BIT_7 | BIT_5));
nv->firmware_options[1] = BIT_7 | BIT_5 | BIT_2;
BIT_5);
if (nv->host_p[0] & BIT_5) {
(icb->special_options[0] | BIT_5);
BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0);
(icb->firmware_options[0] & ~(BIT_5 | BIT_4));
(icb->add_fw_opt[1] | BIT_5 | BIT_4);
icb->add_fw_opt[1] = (uint8_t)(icb->add_fw_opt[1] & ~(BIT_5 | BIT_4));
nv->firmware_options_1[1] = BIT_5;
nv->firmware_options_2[0] = BIT_5;
nv->firmware_options[1] = BIT_7 | BIT_5 | BIT_2;
} else if (pkt->entry_status & BIT_5) {
if (pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2)) {
#define SKD_IOMAP_IOBASE_MAPPED BIT_5
#define SRB_ELS_PKT BIT_5 /* Extended Link Services pkt */
#define TQF_NEED_AUTHENTICATION BIT_5
#define QL_CONFIG_SPACE_SETUP BIT_5
#define POINT_TO_POINT (uint64_t)BIT_5
#define FC_STATE_CHANGE (uint64_t)BIT_5
#define CFG_ENABLE_LINK_DOWN_REPORTING (uint64_t)BIT_5
#define PRLI_W3_INITIATOR_FUNCTION BIT_5
#define MWB_4096_BYTES (BIT_5 | BIT_4)
#define MWB_2048_BYTES BIT_5
#define HC_RISC_PAUSE BIT_5 /* Pause mode bit */
#define HC24_RISC_RESET BIT_5 /* RISC Reset mode bit. */
#define VPO_TARGET_MODE_DISABLED BIT_5
#define IPCF_FIRST_SEQ BIT_5
#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
#define SF_ARQ_DONE BIT_5
#define SF_DATA_IN BIT_5
#define CFO_SKIP_PRLI BIT_5
#define CFO_IMPLICIT_LOGO_ALL BIT_5
#define CF_DATA_IN BIT_5
#define IDC_FUNC_DST_MASK (BIT_5 | BIT_4)
#define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4)
#define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4)
#define MBX_5 BIT_5
#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
#define FO2_ENABLE_SELECTIVE_CLASS_2 BIT_5
#define FO3_STARTUP_OPTS_VALID BIT_5
#define FWATTRIB2_VI BIT_5
#define IMO_DEVICE_FUNCTION_NUMBER BIT_5
#define LINK_CONFIG_PAUSE_MASK (BIT_6 | BIT_5)
#define FLASH4096 BIT_5
#define INIT_SETUP_RINGS BIT_5
#define CFG_CKSUM_HEADER_IPv4 BIT_5
#define FLASH4096 BIT_5
#define RT_IDX_FC_MACH BIT_5
#define CQ_5_NOT_EMPTY BIT_5