BIT_4
#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4
} else if (tm & BIT_4) {
DMEM_WR32(qlt, icb+0x5c, BIT_5 | BIT_4);
BIT_11 | BIT_5 | BIT_4 | BIT_2 | BIT_1 | BIT_0);
DMEM_WR32(qlt, icb+0x64, BIT_4);
BIT_14 | BIT_8 | BIT_7 | BIT_4);
DMEM_WR32(qlt, icb+0x5c, BIT_11 | BIT_5 | BIT_4 |
BIT_4);
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->to_fw[1] = BIT_4;
req1f = (uint8_t)(req1f | BIT_4);
else if (tm & BIT_4)
req1f = (uint8_t)(req1f | BIT_4);
BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
#define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
#define PCI_X_XFER_CTRL (BIT_4 | BIT_5)
} else if (tm & BIT_4) {
(FCOE_B2V_4(src + offset) & BIT_4) ? 1 : 0;
ddi_put8(els_desc->els_handle, &els_entry->sof_type, (uint8_t)BIT_4);
*bptr & (BIT_6 | BIT_5 | BIT_4))) {
(*bptr & ~(BIT_6|BIT_5|BIT_4));
nv->firmware_options_2[1] = BIT_4;
nv->host_p[0] = BIT_4 | BIT_1;
nv->firmware_options_3[2] = BIT_4;
~(BIT_5 | BIT_4));
(icb->firmware_options_2[1] | BIT_4);
(icb->firmware_options_2[1] & ~BIT_4);
~(BIT_6 | BIT_5 | BIT_4));
~(BIT_6 | BIT_5 | BIT_4));
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
if (nv->host_p[0] & BIT_4) {
(icb->firmware_options[0] & ~(BIT_5 | BIT_4));
(icb->firmware_options[1] & ~BIT_4);
(icb->add_fw_opt[1] | BIT_5 | BIT_4);
icb->add_fw_opt[1] = (uint8_t)(icb->add_fw_opt[1] & ~(BIT_5 | BIT_4));
nv->firmware_options_2[1] = BIT_4;
nv->host_p[0] = BIT_4 | BIT_1;
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
} else if (pkt->entry_status & BIT_4) {
if (pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2)) {
(pkt->log.io_param[0] & BIT_4 ? 0 : BIT_0);
mcp->mb[1] = BIT_4;
#define SKD_IOBASE_MAPPED BIT_4
#define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */
#define TQF_RSCN_RCVD BIT_4
#define QL_INTR_ADDED BIT_4
#define ABORT_CMDS_LOOP_DOWN_TMO (uint64_t)BIT_4
#define SUSPENDED_WAKEUP_FLG (uint64_t)BIT_4
#define CFG_ENABLE_TARGET_RESET (uint64_t)BIT_4
#define PRLI_W3_TARGET_FUNCTION BIT_4
#define MWB_4096_BYTES (BIT_5 | BIT_4)
#define MWB_1024_BYTES BIT_4
#define VPO_INITIATOR_MODE_ENABLED BIT_4
#define IPCF_LAST_SEQ BIT_4
#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
#define FCP_CONF_REQ BIT_4
#define SF_GOT_STATUS BIT_4
#define CF_LUN_RESET BIT_4
#define CFO_COND_PLOGI BIT_4
#define CFO_IMPLICIT_LOGO BIT_4
#define CFO_IMPLICIT_PRLO BIT_4
#define IDC_FUNC_DST_MASK (BIT_5 | BIT_4)
#define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4)
#define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4)
#define BBCR_RUNTIME_REJECT BIT_4
#define MBX_4 BIT_4
#define FO1_DISABLE_LIP_F7_SW BIT_4
#define FO3_SEND_N2N_PRLI BIT_4
#define FWATTRIB2_T10_CRC BIT_4
#define IMO_BUS_NUMBER BIT_4
#define LINK_CONFIG_DCBX_ENA BIT_4
#define FLASH2048 BIT_4
#define LED_AMBER_24 BIT_4
#define FTYPE_HPPA BIT_4
#define INIT_PCI_CONFIG_SETUP BIT_4
#define CFG_HW_UNABLE_PSEUDO_HDR_CKSUM BIT_4
#define IDC_REQ_ALL_DEST_FUNC_MASK BIT_4 /* Mailbox 1 */
#define FLASH2048 BIT_4
#define RT_IDX_MCAST_HASH_MATCH BIT_4
#define CQ_4_NOT_EMPTY BIT_4