BIT_3
#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3
#define BCM540X_INT_DUPLEX_CHNG BIT_3
(op == SCMD_READ_G5)) && (task->task_cdb[1] & BIT_3)) {
(op == SCMD_WRITE_G5)) && (task->task_cdb[1] & BIT_3)) {
(op == SCMD_WRITE_G5)) && (task->task_cdb[1] & BIT_3)) {
(op == SCMD_WRITE_G5)) && (task->task_cdb[1] & BIT_3)) {
(task->task_cdb[1] & BIT_3)) {
ffr->ffr_flags[0] |= BIT_3;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->from_fw_mask = BIT_11 | BIT_10 | BIT_6 | BIT_3 | BIT_2 |
mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7;
mcp->to_fw_mask |= BIT_1 | BIT_3;
mcp->to_fw_mask |= BIT_2 | BIT_3 | BIT_7 | BIT_6;
fcp_rsp_iu[10] = (uint8_t)(fcp_rsp_iu[10] | BIT_3);
BIT_3 | BIT_2 | BIT_1)
BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define ENABLE_RISC_INTR BIT_3
#define RISC_PCI_INTR_REQUEST BIT_3
(FCOE_B2V_1(src + offset) & BIT_3) ? 1 : 0;
(FCOE_B2V_4(src + offset) & BIT_3) ? 1 : 0;
nv->host_p[1] = BIT_3 | BIT_2;
if (nv->host_p[1] & BIT_3) {
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
if (data & BIT_3) {
w16 = (uint16_t)(w16 & ~(BIT_3 & BIT_2));
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
if (nv->host_p[1] & BIT_3) {
nv->adapter_features[0] & BIT_3 ?
(icb->firmware_options[0] & ~BIT_3);
(icb->firmware_options[0] | BIT_3);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
nv->host_p[1] = BIT_3 | BIT_2;
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
} else if (pkt->entry_status & BIT_3) {
if (pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2)) {
mcp->mb[10] = (uint16_t)(retry ? BIT_3 : 0);
port_no = (uint8_t)(port_no | BIT_3);
mcp->mb[1] = BIT_3;
#define SKD_CONFIG_SPACE_SETUP BIT_3
#define SRB_POLL BIT_3 /* Poll for completion. */
#define TQF_INITIATOR_DEVICE BIT_3
#define QL_MUTEX_CV_INITED BIT_3
#define INTERRUPTS_ENABLED (uint64_t)BIT_3
#define TASK_DAEMON_IDLE_CHK_FLG (uint64_t)BIT_3
#define MBX_ABORT BIT_3
#define CFG_ENABLE_FULL_LIP_LOGIN (uint64_t)BIT_3
#define IFLG_INTR_MSIX BIT_3
#define PRLI_W3_OBSOLETE_BIT_3 BIT_3
#define QL_FL_PORT BIT_3
#define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3
#define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */
#define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
#define RISC_INT BIT_3 /* RISC interrupt */
#define NV_DATA_IN BIT_3
#define VPO_ENABLED BIT_3
#define VMF_DIAGNOSTIC_FW BIT_3
#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
#define FCP_RESID_UNDER BIT_3
#define SF_XFERRED_DATA BIT_3
#define SF_SIMPLE_Q BIT_3
#define CF_ABORT_TASK_SET BIT_3
#define CF_STAG BIT_3
#define SE_NIC_HEARTHBEAT BIT_3
#define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_FUNC_3 BIT_3
#define IDC_FC_FUNC (BIT_3 | BIT_2)
#define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define MBX_3 BIT_3
#define FO1_CTIO_RETRY BIT_3
#define FWATTRIB2_SB2 BIT_3
#define IMO_QOS_UPDATE BIT_3
#define LINK_CONFIG_LB_MODE_MASK (BIT_3 | BIT_2 | BIT_1)
#define FLASH1024 BIT_3
#define LED_GREEN_24 BIT_3
#define FTYPE_FW BIT_3
#define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3
#define INIT_MAC_ALLOC BIT_3
#define CFG_SUPPORT_MULTICAST BIT_3
#define DUMP_REQUEST_DRIVER BIT_3
#define IDC_REQ_DEST_FUNC_3_MASK BIT_3
#define FLASH1024 BIT_3
#define RT_IDX_MCAST_REG_MATCH BIT_3
#define CQ_3_NOT_EMPTY BIT_3