BIT_2
#define BCM540X_AUX_LINK_PASS BIT_2
#define BCM540X_INT_SPEED_CHNG BIT_2
#define PHY_STATUS_LINK_PASS BIT_2
if (buf[2] & BIT_2) {
if (buf[2] & BIT_2) {
if (buf[2] & BIT_2) {
} else if (tm & BIT_2) {
ffr->ffr_flags[0] |= BIT_2;
mcp->from_fw_mask |= BIT_1 | BIT_2;
BIT_11 | BIT_5 | BIT_4 | BIT_2 | BIT_1 | BIT_0);
BIT_2 | BIT_1 | BIT_0);
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->from_fw_mask = BIT_11 | BIT_10 | BIT_6 | BIT_3 | BIT_2 |
mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7;
mcp->to_fw_mask |= BIT_2 | BIT_3 | BIT_7 | BIT_6;
mcp->from_fw_mask |= BIT_1 | BIT_2;
fcp_rsp_iu[10] = (uint8_t)(fcp_rsp_iu[10] | BIT_2);
else if (tm & BIT_2)
BIT_3 | BIT_2 | BIT_1)
BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define LNF_BFE_DATA BIT_2
#define PCI_64_BIT_SLOT BIT_2
} else if (tm & BIT_2) {
(FCOE_B2V_1(src + offset) & BIT_2) ? 1 : 0;
(FCOE_B2V_4(src + offset) & BIT_2) ? 1 : 0;
nv->firmware_options_1[0] = BIT_2 | BIT_1;
nv->host_p[1] = BIT_3 | BIT_2;
if (nv->host_p[1] & BIT_2) {
(icb->firmware_options_1[1] | BIT_5 | BIT_2);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
(ip_icb->ip_firmware_options[0] | BIT_2);
if (data & BIT_2) {
w16 = (uint16_t)(w16 & ~(BIT_3 & BIT_2));
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
nv->firmware_options[1] = BIT_7 | BIT_5 | BIT_2;
nv->host_p[1] = BIT_2;
if (nv->host_p[1] & BIT_2) {
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0);
(ip_icb->ip_firmware_options[0] | BIT_2 | BIT_0);
(ip_icb->ip_firmware_options[0] | BIT_2);
nv->firmware_options_1[0] = BIT_2 | BIT_1;
nv->host_p[1] = BIT_3 | BIT_2;
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
nv->firmware_options[1] = BIT_7 | BIT_5 | BIT_2;
nv->host_p[1] = BIT_2;
} else if (pkt->entry_status & BIT_2) {
if (pkt->entry_status & (BIT_5 + BIT_4 + BIT_3 + BIT_2)) {
#define SRB_RETRY BIT_2 /* Driver retrying command. */
#define TQF_FABRIC_DEVICE BIT_2
#define QL_DUMP_UPLOADED BIT_2
#define QL_HBA_BUFFER_SETUP BIT_2
#define ONLINE (uint64_t)BIT_2
#define TASK_DAEMON_ALIVE_FLG (uint64_t)BIT_2
#define MBX_INTERRUPT BIT_2
#define CFG_ENABLE_LIP_RESET (uint64_t)BIT_2
#define IFLG_INTR_MSI BIT_2
#define PRLI_W3_OBSOLETE_BIT_2 BIT_2
#define QL_F_PORT BIT_2
#define NV_DATA_OUT BIT_2
#define VPO_ID_NOT_ACQUIRED BIT_2
#define NV_START_BIT BIT_2
#define VMF_DO_NOT_RESET BIT_2
#define CF_DSD_PTR BIT_2
#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
#define FCP_RESID_OVER BIT_2
#define SF_SENT_CMD BIT_2
#define SF_ORDERED_Q BIT_2
#define CF_CLEAR_TASK_SET BIT_2
#define CF_OTAG BIT_2
#define SE_MPI_RISC BIT_2
#define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_FUNC_2 BIT_2
#define IDC_FC_FUNC (BIT_3 | BIT_2)
#define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define MBX_2 BIT_2
#define FWATTRIB2_MID BIT_2
#define IMO_REQ_RSP_Q_ADDR_TLA BIT_2
#define LINK_CONFIG_LB_MODE_MASK (BIT_3 | BIT_2 | BIT_1)
#define FLASH512S BIT_2
#define LED_YELLOW_24 BIT_2
#define FTYPE_EFI BIT_2
#define INIT_DOORBELL_REGS_SETUP BIT_2
#define CFG_RX_COPY_MODE BIT_2
#define DUMP_REQUEST_REGISTER BIT_2
#define IDC_REQ_DEST_FUNC_2_MASK BIT_2
#define FLASH512S BIT_2
#define FLT_ATTR_NEED_DATA_REALOAD BIT_2
#define RT_IDX_MCAST_MATCH BIT_2
#define CQ_2_NOT_EMPTY BIT_2