BIT_14
#define BCM540X_DSP_SEL_CH_2 BIT_14
#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14)
#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14
#define PHY_CTRL_LOOPBACK_MODE BIT_14
BIT_14 | BIT_8 | BIT_7 | BIT_4);
DMEM_WR32(qlt, icb+0x64, BIT_14 | BIT_8 | BIT_7 |
mcp->to_fw_mask |= BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
flags = (uint16_t)(BIT_14 | ((atio[3] & 0xF0) << 5));
flags = (uint16_t)(BIT_14 | ((atio[3] & 0xF0) << 5));
flags |= BIT_14;
if (flags & BIT_14) {
flags = (uint16_t)(BIT_14 |
#define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \
(FCOE_B2V_2(src + offset) & BIT_14) ? 1 : 0;
w16 = (uint16_t)(w16 & ~(BIT_14 | BIT_13 |
#define SKD_MUTEX_INITED BIT_14
#define SRB_IP_PKT BIT_14 /* IP type packet. */
#define QL_FCA_INIT_FM BIT_14
#define FDISC_ENABLED (uint64_t)BIT_14
#define DRIVER_STALL (uint64_t)BIT_14
#define CFG_CTRL_25XX (uint64_t)BIT_14
#define ISP_FUNC_NUM_MASK (BIT_15 | BIT_14)
#define NV_WR_ENABLE BIT_14 /* write enable */
#define VM_END_OF_DATA BIT_14
#define FAC_APPL_ID BIT_14
#define GID_FP_FA_WWPN BIT_14
#define MBX_14 BIT_14
#define FO1_POST_NOTIFY_ACK_IOCB BIT_14
#define FO3_NO_ABORT_IO_ON_LINK_DOWN BIT_14
#define LINK_CONFIG2_BP_AUTO_NEGO_ENA BIT_14
#define INIT_KSTATS BIT_14
#define RST_FO_REG BIT_14
#define RT_IDX_ETH_SKIP2 BIT_14
#define CQ_14_NOT_EMPTY BIT_14