BIT_13
#define BCM540X_DSP_SEL_CH_1 BIT_13
#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14)
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13)
#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)
#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13
#define PHY_AN_AD_1000X_REMOTE_FAULT_OFFLINE BIT_13
#define PHY_AN_AD_1000X_REMOTE_FAULT_AUTONEG_ERR (BIT_12 | BIT_13)
mcp->to_fw_mask |= BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
#define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \
(FCOE_B2V_2(src + offset) & BIT_13) ? 1 : 0;
w16 = (uint16_t)(w16 & ~(BIT_14 | BIT_13 |
(hccr_reg & (BIT_15 | BIT_13 | BIT_11 | BIT_8))) {
#define SKD_CMD_ABORT_TMO BIT_13
#define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */
#define QL_DB_IOBASE_MAPPED BIT_13
#define VP_ENABLED (uint64_t)BIT_13
#define LOOP_DOWN (uint64_t)BIT_13
#define CFG_CTRL_24XX (uint64_t)BIT_13
#define NV_PR_ENABLE BIT_13 /* protection register enable */
#define TF_TARGET_RESET BIT_13
#define GID_FP_SP_SUPPORT BIT_13
#define MBX_13 BIT_13
#define FO1_AE_QUEUE_FULL BIT_13
#define FO1_POST_NOTIFY_ACK_IOCB_2_ATIO BIT_13
#define FO2_ENABLE_FIBRE_LITE BIT_13
#define FWATTRIB2_EX_REL BIT_13
#define IMO_QUEUE_POINTER_SHADOWING BIT_13
#define INIT_MAC_REGISTERED BIT_13
#define RST_FO_MOP BIT_13
#define RT_IDX_ETH_SKIP1 BIT_13
#define CQ_13_NOT_EMPTY BIT_13