BIT_12
#define PHY_ENABLE_CONFIG_AS_MASTER BIT_12
#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12
#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13)
#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12
#define PHY_AN_AD_1000X_REMOTE_FAULT_LINK_FAILURE BIT_12
#define PHY_AN_AD_1000X_REMOTE_FAULT_AUTONEG_ERR (BIT_12 | BIT_13)
if (miireg & BIT_12) {
mcp->to_fw_mask |= BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
#define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \
BIT_12));
#define SKD_SUSPENDED BIT_12
#define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */
#define QL_N_PORT_INFO_CREATED BIT_12
#define FLASH_ERRLOG_MARKER (uint64_t)BIT_12
#define LOOP_RESYNC_ACTIVE (uint64_t)BIT_12
#define CFG_CTRL_22XX (uint64_t)BIT_12
#define TF_LUN_RESET BIT_12
#define GID_FP_VF_SUPPORT BIT_12
#define MBX_12 BIT_12
#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
#define FO3_HOLD_STS_FOR_ABTS_RSP BIT_12
#define IMO_ATIO_QUEUE_SERVICE BIT_12
#define ADAPTER_INIT BIT_12
#define RST_FO_FRB BIT_12
#define RT_IDX_VLAN_FILTER BIT_12
#define CQ_12_NOT_EMPTY BIT_12