BIT_11
#define PHY_CONFIG_AS_MASTER BIT_11
#define PHY_LINK_PARTNER_1000BASET_FULL BIT_11
#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11)
#define BCM540X_DSP_FILTER_FEXT0 BIT_11
#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11
#define PHY_CTRL_LOWER_POWER_MODE BIT_11
#define PHY_AN_AD_ASYM_PAUSE BIT_11
#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
BIT_11 | BIT_5 | BIT_4 | BIT_2 | BIT_1 | BIT_0);
DMEM_WR32(qlt, icb+0x5c, BIT_11 | BIT_5 | BIT_4 |
mcp->to_fw_mask |= BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
mcp->to_fw_mask = BIT_14 | BIT_13 | BIT_12 | BIT_11 |
mcp->from_fw_mask = BIT_11 | BIT_10 | BIT_6 | BIT_3 | BIT_2 |
scsi_status = (uint16_t)(scsi_status | BIT_11);
BIT_11 | BIT_10 | BIT_9 | BIT_8 | \
#define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11)
(hccr_reg & (BIT_15 | BIT_13 | BIT_11 | BIT_8))) {
#define SKD_PATHNAME_ALLOCED BIT_11
#define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */
#define QL_IOMAP_IOBASE_MAPPED BIT_11
#define PARITY_ERROR (uint64_t)BIT_11
#define LOOP_RESYNC_NEEDED (uint64_t)BIT_11
#define CFG_CTRL_63XX (uint64_t)BIT_11
#define IDC_TIMEOUT_MASK (BIT_11 | BIT_10 | BIT_9 | BIT_8)
#define MBX_11 BIT_11
#define FO1_AE_PLOGI_RJT BIT_11
#define FO1_AE_IMMEDIATE_NOTIFY_IOCB BIT_11
#define FWATTRIB2_FCOE BIT_11
#define IMO_MOVE_QUEUE_BASE_ADDRESS BIT_11
#define INIT_MUTEX BIT_11
#define CFG_ENABLE_SPLIT_HEADER BIT_11
#define RT_IDX_VLAN_MATCH BIT_11
#define CQ_11_NOT_EMPTY BIT_11