BIT_10
#define PHY_LINK_PARTNER_1000BASET_HALF BIT_10
#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11)
#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10)
#define BCM540X_DSP_FILTER_NEXT0 BIT_10
#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10
#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_AUX_100BASET4 BIT_10
#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10)
#define BCM540X_AUX_1000BASET_HD (BIT_9 | BIT_10)
#define BCM540X_AUX_1000BASET_FD (BIT_8 | BIT_9 | BIT_10)
#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10
#define PHY_CTRL_ISOLATE_PHY BIT_10
#define PHY_AN_AD_PAUSE_CAPABLE BIT_10
#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
mcp->to_fw_mask |= BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 |
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 |
mcp->from_fw_mask = BIT_11 | BIT_10 | BIT_6 | BIT_3 | BIT_2 |
mcp->to_fw_mask |= BIT_0 | BIT_1 | BIT_9 | BIT_10;
scsi_status = (uint16_t)(scsi_status | BIT_10);
#define OPT_PUREX_ENABLE (BIT_10)
BIT_11 | BIT_10 | BIT_9 | BIT_8 | \
#define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11)
mr.mb[3] = BIT_10;
#define SKD_INTR_ADDED BIT_10
#define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */
#define QL_FCA_ATTACH_DONE BIT_10
#define FW_DUMP_NEEDED (uint64_t)BIT_10
#define ABORT_ISP_ACTIVE (uint64_t)BIT_10
#define CFG_CTRL_23XX (uint64_t)BIT_10
#define TF_CLEAR_TASK_SET BIT_10
#define IDC_TIMEOUT_MASK (BIT_11 | BIT_10 | BIT_9 | BIT_8)
#define GID_FP_NPIV_SUPPORT BIT_10 /* implies FDISC support */
#define MBX_10 BIT_10
#define FO1_ENABLE_PURE_IOCB BIT_10
#define INIT_ADD_SOFT_INTERRUPT BIT_10
#define CFG_SUPPORT_SCATTER_GATHER BIT_10
#define CSR_RP BIT_10
#define RT_IDX_VLAN_TAG BIT_10
#define CQ_10_NOT_EMPTY BIT_10
#define RISC_PAUSED BIT_10