BIT_1
#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1
#define BCM540X_INT_LINK_CHNG BIT_1
if (tm & BIT_1) {
ffr->ffr_flags[0] |= BIT_1;
mcp->to_fw_mask |= BIT_1 | BIT_8;
mcp->from_fw_mask |= BIT_1 | BIT_2;
BIT_11 | BIT_5 | BIT_4 | BIT_2 | BIT_1 | BIT_0);
BIT_2 | BIT_1 | BIT_0);
BIT_1;
mcp->from_fw_mask = BIT_0 | BIT_1;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->from_fw_mask = BIT_0 | BIT_1;
mcp->to_fw[1] = BIT_6 | BIT_1;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->from_fw_mask = BIT_0 | BIT_1;
BIT_1 | BIT_0;
mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7;
mcp->to_fw_mask |= BIT_0 | BIT_1 | BIT_9 | BIT_10;
mcp->to_fw_mask |= BIT_1 | BIT_3;
mcp->from_fw_mask |= BIT_1 | BIT_2;
fcp_rsp_iu[10] = (uint8_t)(fcp_rsp_iu[10] | BIT_1);
if (tm & BIT_1)
BIT_3 | BIT_2 | BIT_1)
BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define LNF_VPD_DATA BIT_1
#define FLASH_WRITE_ENABLE BIT_1
#define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */
if (tm & BIT_1) {
(FCOE_B2V_1(src + offset) & BIT_1) ? 1 : 0;
(FCOE_B2V_4(src + offset) & BIT_1) ? 1 : 0;
nv->firmware_options_1[0] = BIT_2 | BIT_1;
nv->host_p[0] = BIT_4 | BIT_1;
(icb->firmware_options_1[0] | BIT_1);
(icb->firmware_options_3[0] | BIT_1);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
if (data & BIT_1) {
(icb->firmware_options_2[3] & ~(BIT_1 | BIT_0));
icb->global_vp_option[0] = BIT_1;
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
nv->host_p[0] = BIT_1;
(icb->firmware_options[0] | BIT_6 | BIT_1);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
icb->special_options[0] = (uint8_t)(icb->special_options[0] | BIT_1);
nv->firmware_options_1[0] = BIT_2 | BIT_1;
nv->host_p[0] = BIT_4 | BIT_1;
nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
nv->host_p[0] = BIT_1;
} else if (pkt->entry_status & BIT_1) {
} else if (pkt->entry_status & BIT_1) /* FULL flag */ {
(mr->mb[1] | BIT_1);
mcp->mb[1] = BIT_1;
if (reg_status & BIT_1)
#define LOW_POWER_LEVEL (BIT_1 | BIT_0)
#define SKD_SOFT_STATE_ALLOCED BIT_1
#define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */
#define TQF_QUEUE_SUSPENDED BIT_1 /* Queue suspended. */
#define QL_DUMP_VALID BIT_1
#define QL_REGS_MAPPED BIT_1
#define QL_OPENED (uint64_t)BIT_1
#define TASK_DAEMON_SLEEPING_FLG (uint64_t)BIT_1
#define MBX_BUSY_FLG BIT_1
#define CFG_ENABLE_64BIT_ADDRESSING (uint64_t)BIT_1
#define IFLG_INTR_FIXED BIT_1
#define PRLI_W3_READ_FCP_XFR_RDY_DISABLED BIT_1
#define QL_NL_PORT BIT_1
#define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
#define NV_SELECT BIT_1
#define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1
#define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */
#define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */
#define IPCF_TERMINATE_EXCH BIT_1
#define VMF_FORCE_UPDATE_FW BIT_1
#define CF_RD BIT_1
#define RF_BUSY BIT_1 /* Busy */
#define FCP_SNS_LEN_VALID BIT_1
#define SF_GOT_TARGET BIT_1
#define SF_HEAD_OF_Q BIT_1
#define CF_TARGET_RESET BIT_1
#define CF_HTAG BIT_1
#define SE_NIC_1 BIT_1
#define RSCN_AF_MASK (BIT_1 | BIT_0)
#define TEMP_SUPPORT_ISP BIT_1
#define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_FUNC_1 BIT_1
#define IDC_NIC_FUNC (BIT_1 | BIT_0)
#define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define MBX_1 BIT_1
#define FO1_AE_ALL_LIP_RESET BIT_1
#define FO2_REV_LOOPBACK BIT_1
#define FO3_AE_RND_ERROR BIT_1
#define FWATTRIB2_IP BIT_1
#define IMO_RESPONSE_Q_SERVICE BIT_1
#define LFF_NO_PRLI BIT_1
#define PDF_ADISC BIT_1
#define LINK_CONFIG_LB_MODE_MASK (BIT_3 | BIT_2 | BIT_1)
#define FCF_LIST_RETURN_ONE BIT_1
#define FLASH512 BIT_1
#define FTYPE_BIOS BIT_1
#define QL_MGMT_SERVER_LOGIN BIT_1
#define INIT_REGS_SETUP BIT_1
#define NEED_MPI_RESET BIT_1 /* need MPI RISC reset */
#define CFG_JUMBLE_PACKET BIT_1
#define LOW_POWER_LEVEL (BIT_1 | BIT_0)
#define ADAPTER_ERROR BIT_1
#define DUMP_REQUEST_CORE BIT_1
#define IDC_REQ_DEST_FUNC_1_MASK BIT_1
#define FLASH512 BIT_1
#define FLT_ATTR_NEED_FW_RESTART BIT_1
#define RT_IDX_MCAST BIT_1
#define CQ_1_NOT_EMPTY BIT_1