BIT_0
#define PHY_LINK_PARTNER_AUTONEG_ABILITY BIT_0
BIT_11 | BIT_5 | BIT_4 | BIT_2 | BIT_1 | BIT_0);
BIT_2 | BIT_1 | BIT_0);
mcp->to_fw[1] = (uint16_t)(mcp->to_fw[1] | BIT_0);
mcp->to_fw_mask = BIT_0;
mcp->from_fw_mask = BIT_0 | BIT_1;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->from_fw_mask = BIT_0 | BIT_1;
BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0;
mcp->from_fw_mask = BIT_0 | BIT_1;
mcp->to_fw_mask = BIT_0;
BIT_1 | BIT_0;
mcp->to_fw_mask |= BIT_0 | BIT_9;
mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7;
mcp->to_fw_mask |= BIT_0 | BIT_1 | BIT_9 | BIT_10;
mcp->to_fw_mask |= BIT_0;
mcp->from_fw_mask |= BIT_0;
mcp->from_fw_mask |= BIT_0;
nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0);
nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0);
} while (!(data & BIT_0));
BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define LNF_NVRAM_DATA BIT_0
#define CHIP_SOFT_RESET BIT_0
#define PF_ONLY_FLAG BIT_0 /* Physical Function Only */
(FCOE_B2V_1(src + offset) & BIT_0) ? 1 : 0;
(FCOE_B2V_4(src + offset) & BIT_0) ? 1 : 0;
size = ql_pci_config_get32(ha, PCI_CONF_BASE0) & BIT_0 ?
if (!(fdata & BIT_0)) {
if (ha->pci_function_number & BIT_0) {
BIT_0) {
ha2->task_daemon_flags, (options & BIT_0 ? "stalled" :
if (options & BIT_0) {
WRT16_IO_REG(ha, mailbox_in[9], BIT_0);
firmware_options_1[0] & BIT_0) {
BIT_0) {
icb->node_name[0] = (uint8_t)(icb->node_name[0] & ~BIT_0);
icb->port_name[0] = (uint8_t)(icb->node_name[0] | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
if (CFG_IST(ha, CFG_CTRL_81XX) && nv->enhanced_features[0] & BIT_0) {
(uint8_t)(icb->firmware_options[0] & ~BIT_0);
(uint8_t)(icb->firmware_options[0] | BIT_0);
"of %d\n", data, icb->firmware_options[0] & BIT_0 ? 1 : 0);
if (data & BIT_0) {
(uint8_t)(icb->firmware_options_1[0] & ~BIT_0);
(uint8_t)(icb->firmware_options_1[0] | BIT_0);
icb->firmware_options_1[0] & BIT_0 ? 1 : 0);
if (CFG_IST(ha, CFG_CTRL_24XX) && ha->serdes_param[0] & BIT_0) {
(icb->firmware_options_2[3] & ~(BIT_1 | BIT_0));
w16 = (uint16_t)(w16 & ~BIT_0);
(pkt->vpc.vp_index[bit / 8] | BIT_0 << bit % 8);
} while (!(data & BIT_0));
icb->node_name[0] = (uint8_t)(icb->node_name[0] & ~BIT_0);
icb->port_name[0] = (uint8_t)(icb->node_name[0] | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0);
(ip_icb->ip_firmware_options[0] | BIT_2 | BIT_0);
data = (uint16_t)(data | BIT_0);
(uint16_t)(BIT_0));
if (status & BIT_0) {
rval |= BIT_0;
rval |= BIT_0;
if (stat & BIT_0) {
mcp->mb[10] = BIT_0;
mcp->mb[1] = (uint16_t)(tq->loop_id << 8 | BIT_0);
(pkt->log.io_param[0] & BIT_4 ? 0 : BIT_0);
mcp->mb[4] = BIT_0;
mcp->mb[1] = BIT_0;
if (option & BIT_0) {
mcp->mb[2] = BIT_0;
if (!(status & BIT_0)) {
(void) ql_stall_driver(ha, BIT_0);
(void) ql_stall_driver(ha, BIT_0);
if ((flash_status & BIT_0 /* WIP */) == 0)
if ((flash_status & BIT_0 /* WIP */) == 0)
#define LOW_POWER_LEVEL (BIT_1 | BIT_0)
#define SKD_ATTACHED BIT_0
#define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */
#define LQF_UNTAGGED_PENDING BIT_0
#define TQF_TAPE_DEVICE BIT_0
#define QL_DUMPING BIT_0
#define QL_SOFT_STATE_ALLOCED BIT_0
#define FCA_BOUND (uint64_t)BIT_0
#define TASK_DAEMON_STOP_FLG (uint64_t)BIT_0
#define MBX_WANT_FLG BIT_0
#define CFG_CTRL_27XX (uint64_t)BIT_0
#define IFLG_INTR_LEGACY BIT_0
#define PRLI_W3_WRITE_FCP_XFR_RDY_DISABLED BIT_0
#define QL_N_PORT BIT_0
#define ISP_RESET BIT_0 /* ISP soft reset */
#define NX_MBX_CMD BIT_0 /* Mailbox command present */
#define NX_RISC_INT BIT_0 /* RISC interrupt present */
#define NV_CLOCK BIT_0
#define VPO_HARD_ASSIGNED_ID BIT_0
#define PF_ONLY_FLAG BIT_0 /* Physical Function Only */
#define LNF_NVRAM_DATA BIT_0 /* get nvram */
#define VMF_DO_NOT_UPDATE_FW BIT_0
#define CF_WR BIT_0
#define FCP_RSP_LEN_VALID BIT_0
#define SF_GOT_BUS BIT_0
#define SF_ACA_Q BIT_0
#define CF_CLEAR_ACA BIT_0
#define AF_NO_ABTS BIT_0
#define SE_NIC_2 BIT_0
#define RSCN_AF_MASK (BIT_1 | BIT_0)
#define TEMP_SUPPORT_I2C BIT_0
#define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_FUNC_0 BIT_0
#define IDC_NIC_FUNC (BIT_1 | BIT_0)
#define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define MBX_0 BIT_0
#define FO1_AE_ON_LIPF8 BIT_0
#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
#define FO3_ENABLE_EMERG_IOCB BIT_0
#define FO13_LESB_NO_RESET BIT_0
#define FWATTRIB2_CLASS2 BIT_0
#define IMO_DELETE_Q BIT_0
#define LLF_PLOGI BIT_0 /* unconditional PLOGI */
#define LFF_NO_PLOGI BIT_0
#define PDF_PLOGI BIT_0
#define LINK_CONFIG2_JUMBO_FRM_ENA BIT_0
#define FCF_LIST_RETURN_ALL BIT_0
#define FLASH128 BIT_0
#define LED_ACTIVE BIT_0
#define BEACON_ON BIT_0
#define LED_RED BIT_0
#define FTYPE_FCODE BIT_0
#define QL_AEN_TRACKING_ENABLE BIT_0
#define INIT_SOFTSTATE_ALLOC BIT_0
#define NEED_HW_RESET BIT_0 /* need hardware reset */
#define LOW_POWER_LEVEL (BIT_1 | BIT_0)
#define INTERRUPTS_ENABLED BIT_0
#define IDC_REQ_DEST_FUNC_0_MASK BIT_0 /* Mailbox 2 */
#define FLASH128 BIT_0
#define FLT_ATTR_READ_ONLY BIT_0
#define CQ_0_NOT_EMPTY BIT_0