usr/src/boot/libsa/string/strcspn.c

61

bit = BIT(*charset);

usr/src/boot/libsa/string/strcspn.c

67

bit = BIT(*s1);

usr/src/boot/libsa/string/strspn.c

60

bit = BIT(*charset);

usr/src/boot/libsa/string/strspn.c

66

bit = BIT(*s1);

usr/src/cmd/backup/dump/dumpmain.c

1103

if (BIT(UFSROOTINO, nodmap)) /* empty dump check */

usr/src/cmd/backup/dump/dumptape.c

578

if ((BIT(ino, shamap)) && (spcl.c_type == TS_INODE)) {

usr/src/cmd/backup/dump/dumptraverse.c

127

if (BIT(ino, activemap)) {

usr/src/cmd/backup/dump/dumptraverse.c

235

if (BIT(ino, nodmap))

usr/src/cmd/backup/dump/dumptraverse.c

262

if (!BIT(ino, nodmap)) {

usr/src/cmd/backup/dump/dumptraverse.c

273

if (!BIT(ino, nodmap)) {

usr/src/cmd/backup/dump/dumptraverse.c

409

if ((!BIT(ino, nodmap)) && (!BIT(ino, shamap)))

usr/src/cmd/backup/dump/dumptraverse.c

679

if (!BIT(dp->d_ino, dirmap) &&

usr/src/cmd/backup/dump/dumptraverse.c

692

if (BIT(dp->d_ino, nodmap)) {

usr/src/cmd/backup/dump/dumptraverse.c

696

if (BIT(dp->d_ino, dirmap))

usr/src/cmd/backup/dump/dumptraverse.c

70

if (!(fn == add && BIT(ino, nodmap)))

usr/src/cmd/backup/restore/interactive.c

656

if (!dflag && BIT(dp->d_ino, dumpmap) == 0)

usr/src/cmd/backup/restore/interactive.c

839

if (dflag && BIT(fp->fnum, dumpmap) == 0)

usr/src/cmd/backup/restore/restore.c

102

if (BIT(ino, dumpmap) == 0) {

usr/src/cmd/backup/restore/restore.c

140

if (BIT(i, clrimap))

usr/src/cmd/backup/restore/restore.c

196

if (BIT(ino, dumpmap))

usr/src/cmd/backup/restore/restore.c

33

if (BIT(ino, dumpmap) == 0) {

usr/src/cmd/backup/restore/restore.c

516

if (ep == NIL || ep->e_type == LEAF || BIT(i, dumpmap) == 0)

usr/src/cmd/backup/restore/restore.c

54

if (BIT(ino, dumpmap) == 0) {

usr/src/cmd/backup/restore/utilities.c

445

if (ino == 0 || BIT(ino, dumpmap) == 0)

usr/src/cmd/backup/restore/utilities.c

887

if (!dflag && BIT(dp->d_ino, dumpmap) == 0)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa.c

1009

tx = !!(gtk[0] & BIT(2));

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa.c

1413

tx = !!(gtk_ie[0] & BIT(2));

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

24

#define WPA_CIPHER_NONE BIT(0)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

25

#define WPA_CIPHER_WEP40 BIT(1)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

26

#define WPA_CIPHER_WEP104 BIT(2)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

27

#define WPA_CIPHER_TKIP BIT(3)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

28

#define WPA_CIPHER_CCMP BIT(4)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

30

#define WPA_KEY_MGMT_IEEE8021X BIT(0)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

31

#define WPA_KEY_MGMT_PSK BIT(1)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

32

#define WPA_KEY_MGMT_NONE BIT(2)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

33

#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

35

#define WPA_PROTO_WPA BIT(0)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

36

#define WPA_PROTO_RSN BIT(1)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

82

#define WPA_KEY_INFO_TYPE_MASK (BIT(0) | BIT(1) | BIT(2))

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

83

#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

84

#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

85

#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1: Pairwise, 0: Group key */

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

87

#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

89

#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

90

#define WPA_KEY_INFO_TXRX BIT(6) /* group */

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

91

#define WPA_KEY_INFO_ACK BIT(7)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

92

#define WPA_KEY_INFO_MIC BIT(8)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

93

#define WPA_KEY_INFO_SECURE BIT(9)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

94

#define WPA_KEY_INFO_ERROR BIT(10)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

95

#define WPA_KEY_INFO_REQUEST BIT(11)

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

96

#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */

usr/src/cmd/cmd-inet/usr.lib/wpad/wpa_impl.h

98

#define WPA_CAPABILITY_PREAUTH BIT(0)

usr/src/cmd/cxgbetool/cudbg_view.c

1299

rc = field_desc_show(p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1,

usr/src/cmd/lastcomm/lc_utils.c

267

BIT(ASU, 'S');

usr/src/cmd/lastcomm/lc_utils.c

268

BIT(AFORK, 'F');

usr/src/cmd/lp/cmd/lpsched/notify.c

190

#define P(BIT,MSG) if (chkprinter_result & BIT) fdprintf(fd, MSG)

usr/src/cmd/sgs/yacc/common/y1.c

594

if (BIT(pp, j))

usr/src/cmd/sgs/yacc/common/y3.c

81

if (BIT(u->ws.lset, k)) {

usr/src/common/crypto/skein/skein_impl.h

48

#define SKEIN_T1_BIT(BIT) ((BIT) - 64)

usr/src/common/mc/mc-amd/mcamd_rowcol.c

204

if (BIT(rowaddr, abitno) == 0)

usr/src/common/mc/mc-amd/mcamd_rowcol.c

263

if (BIT(coladdr, abitno) == 0)

usr/src/common/mc/mc-amd/mcamd_rowcol_impl.h

53

#define BITVAL(var, num) ((BIT(var, num) >> (num)) & 1ULL)

usr/src/lib/fm/topo/modules/common/fac_prov_ipmi/fac_prov_ipmi.c

1411

#define ISBITSET(MASK, BIT) ((MASK & BIT) == BIT)

usr/src/uts/common/io/arn/arn_ath9k.h

199

ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),

usr/src/uts/common/io/arn/arn_ath9k.h

200

ATH9K_HW_CAP_MIC_AESCCM = BIT(1),

usr/src/uts/common/io/arn/arn_ath9k.h

201

ATH9K_HW_CAP_MIC_CKIP = BIT(2),

usr/src/uts/common/io/arn/arn_ath9k.h

202

ATH9K_HW_CAP_MIC_TKIP = BIT(3),

usr/src/uts/common/io/arn/arn_ath9k.h

203

ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),

usr/src/uts/common/io/arn/arn_ath9k.h

204

ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),

usr/src/uts/common/io/arn/arn_ath9k.h

205

ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),

usr/src/uts/common/io/arn/arn_ath9k.h

206

ATH9K_HW_CAP_VEOL = BIT(7),

usr/src/uts/common/io/arn/arn_ath9k.h

207

ATH9K_HW_CAP_BSSIDMASK = BIT(8),

usr/src/uts/common/io/arn/arn_ath9k.h

208

ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),

usr/src/uts/common/io/arn/arn_ath9k.h

209

ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),

usr/src/uts/common/io/arn/arn_ath9k.h

210

ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),

usr/src/uts/common/io/arn/arn_ath9k.h

211

ATH9K_HW_CAP_HT = BIT(12),

usr/src/uts/common/io/arn/arn_ath9k.h

212

ATH9K_HW_CAP_GTT = BIT(13),

usr/src/uts/common/io/arn/arn_ath9k.h

213

ATH9K_HW_CAP_FASTCC = BIT(14),

usr/src/uts/common/io/arn/arn_ath9k.h

214

ATH9K_HW_CAP_RFSILENT = BIT(15),

usr/src/uts/common/io/arn/arn_ath9k.h

215

ATH9K_HW_CAP_WOW = BIT(16),

usr/src/uts/common/io/arn/arn_ath9k.h

216

ATH9K_HW_CAP_CST = BIT(17),

usr/src/uts/common/io/arn/arn_ath9k.h

217

ATH9K_HW_CAP_ENHANCEDPM = BIT(18),

usr/src/uts/common/io/arn/arn_ath9k.h

218

ATH9K_HW_CAP_AUTOSLEEP = BIT(19),

usr/src/uts/common/io/arn/arn_ath9k.h

219

ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),

usr/src/uts/common/io/arn/arn_ath9k.h

220

ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),

usr/src/uts/common/io/arn/arn_core.h

328

BUF_DATA = BIT(0),

usr/src/uts/common/io/arn/arn_core.h

329

BUF_AGGR = BIT(1),

usr/src/uts/common/io/arn/arn_core.h

330

BUF_AMPDU = BIT(2),

usr/src/uts/common/io/arn/arn_core.h

331

BUF_HT = BIT(3),

usr/src/uts/common/io/arn/arn_core.h

332

BUF_RETRY = BIT(4),

usr/src/uts/common/io/arn/arn_core.h

333

BUF_XRETRY = BIT(5),

usr/src/uts/common/io/arn/arn_core.h

334

BUF_SHORT_PREAMBLE = BIT(6),

usr/src/uts/common/io/arn/arn_core.h

335

BUF_BAR = BIT(7),

usr/src/uts/common/io/arn/arn_core.h

336

BUF_PSPOLL = BIT(8),

usr/src/uts/common/io/arn/arn_core.h

337

BUF_AGGR_BURST = BIT(9),

usr/src/uts/common/io/arn/arn_core.h

338

BUF_CALC_AIRTIME = BIT(10),

usr/src/uts/common/io/arn/arn_core.h

486

#define AGGR_CLEANUP BIT(1)

usr/src/uts/common/io/arn/arn_core.h

487

#define AGGR_ADDBA_COMPLETE BIT(2)

usr/src/uts/common/io/arn/arn_core.h

488

#define AGGR_ADDBA_PROGRESS BIT(3)

usr/src/uts/common/io/arn/arn_core.h

808

#define SC_OP_INVALID BIT(0)

usr/src/uts/common/io/arn/arn_core.h

809

#define SC_OP_BEACONS BIT(1)

usr/src/uts/common/io/arn/arn_core.h

810

#define SC_OP_RXAGGR BIT(2)

usr/src/uts/common/io/arn/arn_core.h

811

#define SC_OP_TXAGGR BIT(3)

usr/src/uts/common/io/arn/arn_core.h

812

#define SC_OP_CHAINMASK_UPDATE BIT(4)

usr/src/uts/common/io/arn/arn_core.h

813

#define SC_OP_FULL_RESET BIT(5)

usr/src/uts/common/io/arn/arn_core.h

814

#define SC_OP_NO_RESET BIT(6)

usr/src/uts/common/io/arn/arn_core.h

815

#define SC_OP_PREAMBLE_SHORT BIT(7)

usr/src/uts/common/io/arn/arn_core.h

816

#define SC_OP_PROTECT_ENABLE BIT(8)

usr/src/uts/common/io/arn/arn_core.h

817

#define SC_OP_RXFLUSH BIT(9)

usr/src/uts/common/io/arn/arn_core.h

818

#define SC_OP_LED_ASSOCIATED BIT(10)

usr/src/uts/common/io/arn/arn_core.h

819

#define SC_OP_RFKILL_REGISTERED BIT(11)

usr/src/uts/common/io/arn/arn_core.h

820

#define SC_OP_RFKILL_SW_BLOCKED BIT(12)

usr/src/uts/common/io/arn/arn_core.h

821

#define SC_OP_RFKILL_HW_BLOCKED BIT(13)

usr/src/uts/common/io/arn/arn_rc.h

238

ATH9K_TX_RC_USE_RTS_CTS = BIT(0),

usr/src/uts/common/io/arn/arn_rc.h

239

ATH9K_TX_RC_USE_CTS_PROTECT = BIT(1),

usr/src/uts/common/io/arn/arn_rc.h

240

ATH9K_TX_RC_USE_SHORT_PREAMBLE = BIT(2),

usr/src/uts/common/io/arn/arn_rc.h

241

ATH9K_TX_RC_MCS = BIT(3),

usr/src/uts/common/io/arn/arn_rc.h

242

ATH9K_TX_RC_GREEN_FIELD = BIT(4),

usr/src/uts/common/io/arn/arn_rc.h

243

ATH9K_TX_RC_40_MHZ_WIDTH = BIT(5),

usr/src/uts/common/io/arn/arn_rc.h

244

ATH9K_TX_RC_DUP_DATA = BIT(6),

usr/src/uts/common/io/arn/arn_rc.h

245

ATH9K_TX_RC_SHORT_GI = BIT(7),

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

100

#define FUNCTRL1_INTRM BIT(5) /* enable MCB intr */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

101

#define FUNCTRL1_BREQ BIT(4) /* bus master enable */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

102

#define FUNCTRL1_VOICE_EN BIT(3)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

103

#define FUNCTRL1_UART_EN BIT(2)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

104

#define FUNCTRL1_JYSTK_EN BIT(1)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

106

#define CHFORMAT_CHB3D5C BIT(31) /* 5 channel surround */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

107

#define CHFORMAT_CHB3D BIT(29) /* 4 channel surround */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

126

#define INTCTRL_TDMA_EN BIT(18)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

127

#define INTCTRL_CH1_EN BIT(17)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

128

#define INTCTRL_CH0_EN BIT(16)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

130

#define INTSTAT_INTR BIT(31)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

131

#define INTSTAT_MCB_INT BIT(26)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

132

#define INTSTAT_UART_INT BIT(16)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

133

#define INTSTAT_LTDMA_INT BIT(15)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

134

#define INTSTAT_HTDMA_INT BIT(14)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

135

#define INTSTAT_LHBTOG BIT(7)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

136

#define INTSTAT_LEGDMA BIT(6)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

137

#define INTSTAT_LEGHIGH BIT(5)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

138

#define INTSTAT_LEGSTEREO BIT(4)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

139

#define INTSTAT_CH1_BUSY BIT(3)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

140

#define INTSTAT_CH0_BUSY BIT(2)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

141

#define INTSTAT_CH1_INT BIT(1)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

142

#define INTSTAT_CH0_INT BIT(0)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

144

#define LEGACY_NXCHG BIT(31)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

145

#define LEGACY_CHB3D6C BIT(15) /* 6 channel surround */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

146

#define LEGACY_CENTR2LN BIT(14) /* line in as center out */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

147

#define LEGACY_BASS2LN BIT(13) /* line in as lfe */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

148

#define LEGACY_EXBASSEN BIT(12) /* external bass input enable */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

150

#define MISC_PWD BIT(31) /* power down */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

151

#define MISC_RESET BIT(30)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

152

#define MISC_N4SPK3D BIT(26) /* 4 channel emulation */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

153

#define MISC_ENDBDAC BIT(23) /* dual dac */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

154

#define MISC_XCHGDAC BIT(22) /* swap front/rear dacs */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

155

#define MISC_SPD32SEL BIT(21) /* 32-bit SPDIF (default 16-bit) */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

156

#define MISC_FM_EN BIT(19) /* enable legacy FM */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

157

#define MISC_SPDF_AC97 BIT(15) /* spdif out 44.1k (0), 48 k (1) */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

158

#define MISC_ENCENTER BIT(7) /* enable center */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

159

#define MISC_REAR2LN BIT(6) /* send rear to line in */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

161

#define MIX2_FMMUTE BIT(7)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

162

#define MIX2_WSMUTE BIT(6)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

163

#define MIX2_SPK4 BIT(5) /* line-in is rear out */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

164

#define MIX2_REAR2FRONT BIT(4) /* swap front and rear */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

165

#define MIX2_WAVEIN_L BIT(3) /* for recording wave out */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

166

#define MIX2_WAVEIN_R BIT(2) /* for recording wave out */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

167

#define MIX2_X3DEN BIT(1) /* 3D surround enable */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

168

#define MIX2_CDPLAY BIT(0) /* spdif-in PCM to DAC */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

170

#define MIX3_RAUXREN BIT(7)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

171

#define MIX3_RAUXLEN BIT(6)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

172

#define MIX3_VAUXRM BIT(5) /* r-aux mute */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

173

#define MIX3_VAUXLM BIT(4) /* l-aux mute */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

175

#define MIX3_CEN2MIC BIT(2)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

176

#define MIX3_MICGAINZ BIT(0) /* mic gain */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

181

#define MISC2_CHB3D8C BIT(5) /* 8 channel surround */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

182

#define MISC2_SPD32FMT BIT(4) /* spdif at 32 kHz */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

183

#define MISC2_ADC2SPDIF BIT(3) /* send adc to spdif out */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

184

#define MISC2_SHAREADC BIT(2) /* use adc for cen/lfe */

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

224

#define EXTENSION_VPHONE_MUTE BIT(4)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

225

#define EXTENSION_BEEPER_MUTE BIT(3)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

226

#define EXTENSION_VADCMIC3 BIT(0)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

73

#define FUNCTRL0_CH1_RST BIT(19)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

74

#define FUNCTRL0_CH0_RST BIT(18)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

75

#define FUNCTRL0_CH1_EN BIT(17)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

76

#define FUNCTRL0_CH0_EN BIT(16)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

77

#define FUNCTRL0_CH1_PAUSE BIT(3)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

78

#define FUNCTRL0_CH0_PAUSE BIT(2)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

79

#define FUNCTRL0_CH1_REC BIT(1)

usr/src/uts/common/io/audio/drv/audiocmi/audiocmi.h

80

#define FUNCTRL0_CH0_REC BIT(0)

usr/src/uts/common/io/ena/ena_aenq.c

112

bool supported = BIT(grpstr->eag_type) &

usr/src/uts/common/io/ena/ena_aenq.c

114

bool enabled = BIT(grpstr->eag_type) &

usr/src/uts/common/io/ena/ena_aenq.c

84

to_enable = BIT(ENAHW_AENQ_GROUP_LINK_CHANGE) |

usr/src/uts/common/io/ena/ena_aenq.c

85

BIT(ENAHW_AENQ_GROUP_FATAL_ERROR) |

usr/src/uts/common/io/ena/ena_aenq.c

86

BIT(ENAHW_AENQ_GROUP_WARNING) |

usr/src/uts/common/io/ena/ena_aenq.c

87

BIT(ENAHW_AENQ_GROUP_NOTIFICATION) |

usr/src/uts/common/io/ena/ena_aenq.c

88

BIT(ENAHW_AENQ_GROUP_KEEP_ALIVE) |

usr/src/uts/common/io/ena/ena_aenq.c

89

BIT(ENAHW_AENQ_GROUP_DEVICE_REQUEST_RESET);

usr/src/uts/common/io/ena/ena_hw.h

1045

#define ENAHW_CMD_PHASE_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

1310

#define ENAHW_FEAT_LINK_CONF_AUTONEG_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

1312

#define ENAHW_FEAT_LINK_CONF_DUPLEX_MASK BIT(1)

usr/src/uts/common/io/ena/ena_hw.h

1362

#define ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

1364

#define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_MASK BIT(1)

usr/src/uts/common/io/ena/ena_hw.h

1366

#define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)

usr/src/uts/common/io/ena/ena_hw.h

1368

#define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_MASK BIT(3)

usr/src/uts/common/io/ena/ena_hw.h

1370

#define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)

usr/src/uts/common/io/ena/ena_hw.h

1372

#define ENAHW_FEAT_OFFLOAD_TSO_IPV4_MASK BIT(5)

usr/src/uts/common/io/ena/ena_hw.h

1374

#define ENAHW_FEAT_OFFLOAD_TSO_IPV6_MASK BIT(6)

usr/src/uts/common/io/ena/ena_hw.h

1376

#define ENAHW_FEAT_OFFLOAD_TSO_ECN_MASK BIT(7)

usr/src/uts/common/io/ena/ena_hw.h

1377

#define ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

1379

#define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_MASK BIT(1)

usr/src/uts/common/io/ena/ena_hw.h

1381

#define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_MASK BIT(2)

usr/src/uts/common/io/ena/ena_hw.h

1383

#define ENAHW_FEAT_OFFLOAD_RX_HASH_MASK BIT(3)

usr/src/uts/common/io/ena/ena_hw.h

1783

#define ENAHW_TX_DESC_META_DESC_MASK BIT(23)

usr/src/uts/common/io/ena/ena_hw.h

1785

#define ENAHW_TX_DESC_PHASE_MASK BIT(24)

usr/src/uts/common/io/ena/ena_hw.h

1787

#define ENAHW_TX_DESC_FIRST_MASK BIT(26)

usr/src/uts/common/io/ena/ena_hw.h

1789

#define ENAHW_TX_DESC_LAST_MASK BIT(27)

usr/src/uts/common/io/ena/ena_hw.h

1791

#define ENAHW_TX_DESC_COMP_REQ_MASK BIT(28)

usr/src/uts/common/io/ena/ena_hw.h

1794

#define ENAHW_TX_DESC_DF_MASK BIT(4)

usr/src/uts/common/io/ena/ena_hw.h

1796

#define ENAHW_TX_DESC_TSO_EN_MASK BIT(7)

usr/src/uts/common/io/ena/ena_hw.h

1800

#define ENAHW_TX_DESC_L3_CSUM_EN_MASK BIT(13)

usr/src/uts/common/io/ena/ena_hw.h

1802

#define ENAHW_TX_DESC_L4_CSUM_EN_MASK BIT(14)

usr/src/uts/common/io/ena/ena_hw.h

1804

#define ENAHW_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)

usr/src/uts/common/io/ena/ena_hw.h

1806

#define ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)

usr/src/uts/common/io/ena/ena_hw.h

1939

#define ENAHW_TX_META_DESC_EXT_VALID_MASK BIT(14)

usr/src/uts/common/io/ena/ena_hw.h

1943

#define ENAHW_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)

usr/src/uts/common/io/ena/ena_hw.h

1945

#define ENAHW_TX_META_DESC_META_STORE_MASK BIT(21)

usr/src/uts/common/io/ena/ena_hw.h

1947

#define ENAHW_TX_META_DESC_META_DESC_MASK BIT(23)

usr/src/uts/common/io/ena/ena_hw.h

1949

#define ENAHW_TX_META_DESC_PHASE_MASK BIT(24)

usr/src/uts/common/io/ena/ena_hw.h

1950

#define ENAHW_TX_META_DESC_FIRST_MASK BIT(26)

usr/src/uts/common/io/ena/ena_hw.h

1951

#define ENAHW_TX_META_DESC_LAST_MASK BIT(27)

usr/src/uts/common/io/ena/ena_hw.h

1952

#define ENAHW_TX_META_DESC_COMP_REQ_MASK BIT(28)

usr/src/uts/common/io/ena/ena_hw.h

2027

#define ENAHW_TX_CDESC_PHASE_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

2074

#define ENAHW_RX_DESC_PHASE_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

2076

#define ENAHW_RX_DESC_FIRST_MASK BIT(2)

usr/src/uts/common/io/ena/ena_hw.h

2078

#define ENAHW_RX_DESC_LAST_MASK BIT(3)

usr/src/uts/common/io/ena/ena_hw.h

2080

#define ENAHW_RX_DESC_COMP_REQ_MASK BIT(4)

usr/src/uts/common/io/ena/ena_hw.h

2178

#define ENAHW_RX_CDESC_L3_CSUM_ERR_MASK BIT(13)

usr/src/uts/common/io/ena/ena_hw.h

2180

#define ENAHW_RX_CDESC_L4_CSUM_ERR_MASK BIT(14)

usr/src/uts/common/io/ena/ena_hw.h

2182

#define ENAHW_RX_CDESC_IPV4_FRAG_MASK BIT(15)

usr/src/uts/common/io/ena/ena_hw.h

2184

#define ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK BIT(16)

usr/src/uts/common/io/ena/ena_hw.h

2186

#define ENAHW_RX_CDESC_PHASE_MASK BIT(24)

usr/src/uts/common/io/ena/ena_hw.h

2188

#define ENAHW_RX_CDESC_L3_CSUM2_MASK BIT(25)

usr/src/uts/common/io/ena/ena_hw.h

2190

#define ENAHW_RX_CDESC_FIRST_MASK BIT(26)

usr/src/uts/common/io/ena/ena_hw.h

2192

#define ENAHW_RX_CDESC_LAST_MASK BIT(27)

usr/src/uts/common/io/ena/ena_hw.h

2194

#define ENAHW_RX_CDESC_BUFFER_MASK BIT(30)

usr/src/uts/common/io/ena/ena_hw.h

2234

#define ENAHW_REG_INTR_UNMASK_MASK BIT(30)

usr/src/uts/common/io/ena/ena_hw.h

339

#define ENAHW_AENQ_DESC_PHASE_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

344

#define ENAHW_AENQ_LINK_CHANGE_LINK_STATUS_MASK BIT(0)

usr/src/uts/common/io/ena/ena_hw.h

501

ENAHW_LLQ_HEADER_INLINE = BIT(0),

usr/src/uts/common/io/ena/ena_hw.h

504

ENAHW_LLQ_HEADER_SEPARATE_RING = BIT(1),

usr/src/uts/common/io/ena/ena_hw.h

515

ENAHW_LLQ_ENTRY_SIZE_128B = BIT(0),

usr/src/uts/common/io/ena/ena_hw.h

516

ENAHW_LLQ_ENTRY_SIZE_192B = BIT(1),

usr/src/uts/common/io/ena/ena_hw.h

517

ENAHW_LLQ_ENTRY_SIZE_256B = BIT(2),

usr/src/uts/common/io/ena/ena_hw.h

531

ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_1 = BIT(0),

usr/src/uts/common/io/ena/ena_hw.h

532

ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_2 = BIT(1),

usr/src/uts/common/io/ena/ena_hw.h

533

ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_4 = BIT(2),

usr/src/uts/common/io/ena/ena_hw.h

534

ENAHW_LLQ_NUM_DESCS_BEFORE_HEADER_8 = BIT(3),

usr/src/uts/common/io/ena/ena_hw.h

548

ENAHW_LLQ_SINGLE_DESC_PER_ENTRY = BIT(0),

usr/src/uts/common/io/ena/ena_hw.h

549

ENAHW_LLQ_MULTIPLE_DESCS_PER_ENTRY = BIT(1),

usr/src/uts/common/io/ena/ena_hw.h

567

ENAHW_LLQ_ACCEL_MODE_DISABLE_META_CACHING = BIT(0),

usr/src/uts/common/io/ena/ena_hw.h

568

ENAHW_LLQ_ACCEL_MODE_LIMIT_TX_BURST = BIT(1),

usr/src/uts/common/io/ena/ena_hw.h

731

#define ENAHW_HOST_INFO_RX_OFFSET_MASK BIT(1)

usr/src/uts/common/io/ena/ena_hw.h

733

#define ENAHW_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)

usr/src/uts/common/io/ena/ena_hw.h

735

#define ENAHW_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)

usr/src/uts/common/io/ena/ena_hw.h

737

#define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)

usr/src/uts/common/io/ena/ena_hw.h

739

#define ENAHW_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)

usr/src/uts/common/io/ena/ena_hw.h

741

#define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7)

usr/src/uts/common/io/ena/ena_hw.h

743

#define ENAHW_HOST_INFO_INFO_PHC_MASK BIT(8)

usr/src/uts/common/io/ena/ena_hw.h

812

#define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_MASK (BIT(5))

usr/src/uts/common/io/ena/ena_hw.h

932

#define ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG_MASK BIT(0)

usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h

2089

#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)

usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h

2090

#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)

usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h

2091

#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)

usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h

2092

#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)

usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h

2093

#define I40E_AQ_SET_FEC_AUTO BIT(4)

usr/src/uts/common/io/i40e/core/i40e_common.c

1546

#define I40E_FW_LED BIT(4)

usr/src/uts/common/io/i40e/core/i40e_common.c

1664

gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);

usr/src/uts/common/io/i40e/core/i40e_common.c

1666

gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);

usr/src/uts/common/io/i40e/core/i40e_dcb.c

1042

maxtcwilling = BIT(I40E_IEEE_ETS_WILLING_SHIFT);

usr/src/uts/common/io/i40e/core/i40e_dcb.c

1177

buf[0] = BIT(I40E_IEEE_PFC_WILLING_SHIFT);

usr/src/uts/common/io/i40e/core/i40e_dcb.c

1180

buf[0] |= BIT(I40E_IEEE_PFC_MBC_SHIFT);

usr/src/uts/common/io/i40e/core/i40e_dcb.c

408

if (app->prio_map & BIT(up))

usr/src/uts/common/io/i40e/core/i40e_dcb.h

115

#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)

usr/src/uts/common/io/i40e/core/i40e_dcb.h

117

#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)

usr/src/uts/common/io/i40e/core/i40e_dcb.h

92

#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)

usr/src/uts/common/io/i40e/core/i40e_dcb.h

94

#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)

usr/src/uts/common/io/i40e/core/i40e_hmc.h

138

BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \

usr/src/uts/common/io/i40e/core/i40e_lan_hmc.c

1001

mask = BIT(ce_info->width) - 1;

usr/src/uts/common/io/i40e/core/i40e_lan_hmc.c

1051

mask = BIT(ce_info->width) - 1;

usr/src/uts/common/io/i40e/core/i40e_lan_hmc.c

778

mask = (u8)(BIT(ce_info->width) - 1);

usr/src/uts/common/io/i40e/core/i40e_lan_hmc.c

819

mask = BIT(ce_info->width) - 1;

usr/src/uts/common/io/i40e/core/i40e_lan_hmc.c

869

mask = BIT(ce_info->width) - 1;

usr/src/uts/common/io/i40e/core/i40e_lan_hmc.c

963

mask = (u8)(BIT(ce_info->width) - 1);

usr/src/uts/common/io/i40e/core/i40e_nvm.c

227

BIT(I40E_GLNVM_SRCTL_START_SHIFT);

usr/src/uts/common/io/i40e/core/i40e_nvm.c

63

nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;

usr/src/uts/common/io/i40e/core/i40e_type.h

1560

#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)

usr/src/uts/common/io/i40e/core/i40e_type.h

1561

#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)

usr/src/uts/common/io/i40e/core/i40e_type.h

1562

#define I40E_PTR_TYPE BIT(15)

usr/src/uts/common/io/i40e/core/i40e_type.h

1564

#define I40E_SR_OCP_ENABLED BIT(15)

usr/src/uts/common/io/i40e/core/i40e_type.h

1742

#define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8)

usr/src/uts/common/io/i40e/core/i40e_type.h

1743

#define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9)

usr/src/uts/common/io/i40e/core/i40e_type.h

558

#define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0)

usr/src/uts/common/io/i40e/core/i40e_type.h

898

#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \

usr/src/uts/common/io/i40e/core/virtchnl.h

91

VIRTCHNL_LINK_SPEED_100MB = BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

92

VIRTCHNL_LINK_SPEED_1GB = BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

93

VIRTCHNL_LINK_SPEED_10GB = BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

94

VIRTCHNL_LINK_SPEED_40GB = BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

95

VIRTCHNL_LINK_SPEED_20GB = BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

96

VIRTCHNL_LINK_SPEED_25GB = BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

97

VIRTCHNL_LINK_SPEED_2_5GB = BIT(VIRTCHNL_LINK_SPEED_2_5GB_SHIFT),

usr/src/uts/common/io/i40e/core/virtchnl.h

98

VIRTCHNL_LINK_SPEED_5GB = BIT(VIRTCHNL_LINK_SPEED_5GB_SHIFT),

usr/src/uts/common/io/ixgbe/core/ixgbe_e610.c

3166

flash->sr_words = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB;

usr/src/uts/common/io/ixgbe/core/ixgbe_e610.c

5094

eeprom->word_size = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB;

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1003

#define IXGBE_ACI_LINK_25G_KR_FEC_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1004

#define IXGBE_ACI_LINK_25G_RS_528_FEC_EN BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1005

#define IXGBE_ACI_LINK_25G_RS_544_FEC_EN BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1010

#define IXGBE_ACI_CFG_PACING_TYPE_M BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1024

#define IXGBE_ACI_LINK_SPEED_10MB BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1025

#define IXGBE_ACI_LINK_SPEED_100MB BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1026

#define IXGBE_ACI_LINK_SPEED_1000MB BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1027

#define IXGBE_ACI_LINK_SPEED_2500MB BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1028

#define IXGBE_ACI_LINK_SPEED_5GB BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1029

#define IXGBE_ACI_LINK_SPEED_10GB BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1030

#define IXGBE_ACI_LINK_SPEED_20GB BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1031

#define IXGBE_ACI_LINK_SPEED_25GB BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1032

#define IXGBE_ACI_LINK_SPEED_40GB BIT(8)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1033

#define IXGBE_ACI_LINK_SPEED_50GB BIT(9)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1034

#define IXGBE_ACI_LINK_SPEED_100GB BIT(10)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1035

#define IXGBE_ACI_LINK_SPEED_200GB BIT(11)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1036

#define IXGBE_ACI_LINK_SPEED_UNKNOWN BIT(15)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1039

#define IXGBE_ACI_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1047

#define IXGBE_ACI_LINK_LP_10G_KR_FEC_CAP BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1048

#define IXGBE_ACI_LINK_LP_25G_KR_FEC_CAP BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1049

#define IXGBE_ACI_LINK_LP_RS_528_FEC_CAP BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1050

#define IXGBE_ACI_LINK_LP_50G_KR_272_FEC_CAP BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1051

#define IXGBE_ACI_LINK_LP_100G_KR_272_FEC_CAP BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1052

#define IXGBE_ACI_LINK_LP_200G_KR_272_FEC_CAP BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1054

#define IXGBE_ACI_LINK_LP_10G_KR_FEC_REQ BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1055

#define IXGBE_ACI_LINK_LP_25G_KR_FEC_REQ BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1056

#define IXGBE_ACI_LINK_LP_RS_528_FEC_REQ BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1057

#define IXGBE_ACI_LINK_LP_KR_272_FEC_REQ BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1059

#define IXGBE_ACI_LINK_LP_PAUSE_ADV BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1060

#define IXGBE_ACI_LINK_LP_ASM_DIR_ADV BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1071

#define IXGBE_ACI_LINK_EVENT_UPDOWN BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1072

#define IXGBE_ACI_LINK_EVENT_MEDIA_NA BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1073

#define IXGBE_ACI_LINK_EVENT_LINK_FAULT BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1074

#define IXGBE_ACI_LINK_EVENT_PHY_TEMP_ALARM BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1075

#define IXGBE_ACI_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1076

#define IXGBE_ACI_LINK_EVENT_SIGNAL_DETECT BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1077

#define IXGBE_ACI_LINK_EVENT_AN_COMPLETED BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1078

#define IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1079

#define IXGBE_ACI_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1080

#define IXGBE_ACI_LINK_EVENT_TOPO_CONFLICT BIT(10)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1081

#define IXGBE_ACI_LINK_EVENT_MEDIA_CONFLICT BIT(11)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1082

#define IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1091

#define IXGBE_ACI_LINK_TOPO_PORT_NUM_VALID BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1126

#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1127

#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1162

#define IXGBE_ACI_I2C_ADDR_TYPE_M BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1167

#define IXGBE_ACI_I2C_USE_REPEATED_START BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1190

#define IXGBE_ACI_MDIO_CLAUSE_22 BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1191

#define IXGBE_ACI_MDIO_CLAUSE_45 BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1209

#define IXGBE_ACI_GPIO_ON BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1220

#define IXGBE_ACI_PORT_ID_PORT_NUM_VALID BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1222

#define IXGBE_ACI_PORT_IDENT_LED_BLINK BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1245

#define IXGBE_ACI_SFF_PORT_NUM_VALID BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1249

#define IXGBE_ACI_SFF_I2CBUS_TYPE_M BIT(10)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1258

#define IXGBE_ACI_SFF_IS_WRITE BIT(15)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1297

#define IXGBE_ACI_NVM_LAST_CMD BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1298

#define IXGBE_ACI_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1302

#define IXGBE_ACI_NVM_PRESERVE_ALL BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1305

#define IXGBE_ACI_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1306

#define IXGBE_ACI_NVM_ACTIV_SEL_OROM BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1307

#define IXGBE_ACI_NVM_ACTIV_SEL_NETLIST BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1308

#define IXGBE_ACI_NVM_SPECIAL_UPDATE BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1309

#define IXGBE_ACI_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

131

#define E610_SR_POINTER_TYPE_BIT BIT(15)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1311

#define IXGBE_ACI_NVM_FLASH_ONLY BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1316

#define IXGBE_ACI_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1322

#define IXGBE_ACI_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1339

#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_M BIT(15)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1363

#define IXGBE_ACI_NVM_MINSREV_NVM_VALID BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1364

#define IXGBE_ACI_NVM_MINSREV_OROM_VALID BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1376

#define IXGBE_ACI_ANVM_MULTIPLE_ELEMS BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1377

#define IXGBE_ACI_ANVM_IMMEDIATE_FIELD BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1378

#define IXGBE_ACI_ANVM_NEW_CFG BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1400

#define IXGBE_ACI_NVM_CHECKSUM_VERIFY BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1401

#define IXGBE_ACI_NVM_CHECKSUM_RECALC BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1414

#define IXGBE_ACI_SANITIZE_REQ_OPERATE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1417

#define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_STATE BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1420

#define IXGBE_ACI_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1421

#define IXGBE_ACI_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1422

#define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1423

#define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1424

#define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_DONE BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1425

#define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1426

#define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1427

#define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1428

#define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1429

#define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1458

#define IXGBE_ACI_CMD_UEFI_BIOS_MODE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1459

#define IXGBE_ACI_RESP_RESET_NEEDED BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1488

#define IXGBE_ACI_NODE_HANDLE_VALID BIT(10)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1497

#define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1498

#define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1500

#define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1501

#define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1515

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_LOS BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1516

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1517

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1518

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1519

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1520

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1521

#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1523

#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1524

#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_GPS BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1525

#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1526

#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_PHY BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1528

#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1529

#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1530

#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1531

#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1535

#define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1536

#define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1547

#define IXGBE_ACI_SET_CGU_OUT_CFG_OUT_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1548

#define IXGBE_ACI_SET_CGU_OUT_CFG_ESYNC_EN BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1549

#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1550

#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1551

#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1567

#define IXGBE_ACI_GET_CGU_OUT_CFG_OUT_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1568

#define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_EN BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1569

#define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1590

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1591

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1592

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1593

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1594

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1595

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1596

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1598

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1599

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1600

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1601

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1602

#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1625

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1626

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1627

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1628

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1629

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1630

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1631

#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1716

#define IXGBE_ACI_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1717

#define IXGBE_ACI_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1718

#define IXGBE_ACI_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1867

#define IXGBE_FWLOG_OPTION_ARQ_ENA BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1868

#define IXGBE_FWLOG_OPTION_UART_ENA BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1872

#define IXGBE_FWLOG_OPTION_REGISTER_ON_INIT BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1876

#define IXGBE_FWLOG_OPTION_IS_REGISTERED BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1907

#define IXGBE_ACI_FW_LOG_CONF_UART_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1908

#define IXGBE_ACI_FW_LOG_CONF_AQ_EN BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1909

#define IXGBE_ACI_FW_LOG_QUERY_REGISTERED BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1910

#define IXGBE_ACI_FW_LOG_CONF_SET_VALID BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1911

#define IXGBE_ACI_FW_LOG_AQ_REGISTER BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1912

#define IXGBE_ACI_FW_LOG_AQ_QUERY BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1913

#define IXGBE_ACI_FW_LOG_PERSISTENT BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

1915

#define IXGBE_ACI_FW_LOG_MORE_DATA BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

197

#define IXGBE_SR_CTRL_WORD_OROM_BANK BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

198

#define IXGBE_SR_CTRL_WORD_NETLIST_BANK BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

199

#define IXGBE_SR_CTRL_WORD_NVM_BANK BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

200

#define IXGBE_SR_NVM_PTR_4KB_UNITS BIT(15)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2054

#define IXGBE_MGMT_MODE_PROTO_RSVD BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2055

#define IXGBE_MGMT_MODE_PROTO_PLDM BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2056

#define IXGBE_MGMT_MODE_PROTO_OEM BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2057

#define IXGBE_MGMT_MODE_PROTO_NC_SI BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2109

#define IXGBE_WOL_SUPPORT_M BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2110

#define IXGBE_ACPI_PROG_MTHD_M BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2111

#define IXGBE_PROXY_SUPPORT_M BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2119

#define IXGBE_NVM_MGMT_SEC_REV_DISABLED BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2120

#define IXGBE_NVM_MGMT_UPDATE_DISABLED BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2121

#define IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2122

#define IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2138

#define IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

2140

#define IXGBE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

225

#define GL_FWSTS_FWROWD_M BIT(8)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

227

#define GL_FWSTS_FWRI_M BIT(9)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

230

#define GL_FWSTS_EP_PF0 BIT(24)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

231

#define GL_FWSTS_EP_PF1 BIT(25)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

248

#define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

252

#define GL_MNG_FWSM_RSV2_M BIT(15)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

254

#define GL_MNG_FWSM_PCIR_AL_FAILURE_M BIT(16)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

256

#define GL_MNG_FWSM_POR_AL_FAILURE_M BIT(17)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

258

#define GL_MNG_FWSM_RSV3_M BIT(18)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

262

#define GL_MNG_FWSM_RSV4_M BIT(25)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

269

#define GL_MNG_FWSM_FW_MODES_DEBUG_M BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

270

#define GL_MNG_FWSM_FW_MODES_RECOVERY_M BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

271

#define GL_MNG_FWSM_FW_MODES_ROLLBACK_M BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

276

#define GLNVM_GENS_NVM_PRES_M BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

280

#define GLNVM_GENS_BANK1VAL_M BIT(8)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

282

#define GLNVM_GENS_ALT_PRST_M BIT(23)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

284

#define GLNVM_GENS_FL_AUTO_RD_M BIT(25)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

289

#define GLNVM_FLA_LOCKED_M BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

295

#define RDASB_MSGCTL_CMDV_M BIT(31)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

297

#define RDASB_RSPCTL_BAD_LENGTH_M BIT(30)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

298

#define RDASB_RSPCTL_NOT_SUCCESS_M BIT(31)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

318

#define SPISB_MSGCTL_CMDV_M BIT(31)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

320

#define SPISB_RSPCTL_BAD_LENGTH_M BIT(30)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

321

#define SPISB_RSPCTL_NOT_SUCCESS_M BIT(31)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

345

#define PF_HICR_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

346

#define PF_HICR_C BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

347

#define PF_HICR_SV BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

348

#define PF_HICR_EV BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

358

#define GL_HICR_C BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

359

#define GL_HICR_SV BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

360

#define GL_HICR_EV BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

364

#define GL_HICR_EN_CHECK BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

40

#ifndef BIT

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

417

#define IXGBE_ACI_FLAG_DD BIT(IXGBE_ACI_FLAG_DD_S) /* 0x1 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

418

#define IXGBE_ACI_FLAG_CMP BIT(IXGBE_ACI_FLAG_CMP_S) /* 0x2 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

419

#define IXGBE_ACI_FLAG_ERR BIT(IXGBE_ACI_FLAG_ERR_S) /* 0x4 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

420

#define IXGBE_ACI_FLAG_VFE BIT(IXGBE_ACI_FLAG_VFE_S) /* 0x8 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

421

#define IXGBE_ACI_FLAG_LB BIT(IXGBE_ACI_FLAG_LB_S) /* 0x200 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

422

#define IXGBE_ACI_FLAG_RD BIT(IXGBE_ACI_FLAG_RD_S) /* 0x400 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

423

#define IXGBE_ACI_FLAG_VFC BIT(IXGBE_ACI_FLAG_VFC_S) /* 0x800 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

424

#define IXGBE_ACI_FLAG_BUF BIT(IXGBE_ACI_FLAG_BUF_S) /* 0x1000 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

425

#define IXGBE_ACI_FLAG_SI BIT(IXGBE_ACI_FLAG_SI_S) /* 0x2000 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

426

#define IXGBE_ACI_FLAG_EI BIT(IXGBE_ACI_FLAG_EI_S) /* 0x4000 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

427

#define IXGBE_ACI_FLAG_FE BIT(IXGBE_ACI_FLAG_FE_S) /* 0x8000 */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

749

#define IXGBE_ACI_GET_FW_EVENT_STATUS_OBTAINED BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

750

#define IXGBE_ACI_GET_FW_EVENT_STATUS_PENDING BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

762

#define IXGBE_ACI_GET_PHY_RQM BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

773

#define IXGBE_ACI_REPORT_TOPO_CAP_MEDIA BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

774

#define IXGBE_ACI_REPORT_ACTIVE_CFG BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

775

#define IXGBE_ACI_REPORT_DFLT_CFG BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

821

#define IXGBE_ACI_PHY_EN_TX_LINK_PAUSE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

822

#define IXGBE_ACI_PHY_EN_RX_LINK_PAUSE BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

823

#define IXGBE_ACI_PHY_LOW_POWER_MODE BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

824

#define IXGBE_ACI_PHY_EN_LINK BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

825

#define IXGBE_ACI_PHY_AN_MODE BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

826

#define IXGBE_ACI_PHY_EN_MOD_QUAL BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

827

#define IXGBE_ACI_PHY_EN_LESM BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

828

#define IXGBE_ACI_PHY_EN_AUTO_FEC BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

831

#define IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

832

#define IXGBE_ACI_PHY_AN_EN_CLAUSE28 BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

833

#define IXGBE_ACI_PHY_AN_EN_CLAUSE73 BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

834

#define IXGBE_ACI_PHY_AN_EN_CLAUSE37 BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

836

#define IXGBE_ACI_PHY_EEE_EN_100BASE_TX BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

837

#define IXGBE_ACI_PHY_EEE_EN_1000BASE_T BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

838

#define IXGBE_ACI_PHY_EEE_EN_10GBASE_T BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

839

#define IXGBE_ACI_PHY_EEE_EN_1000BASE_KX BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

840

#define IXGBE_ACI_PHY_EEE_EN_10GBASE_KR BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

841

#define IXGBE_ACI_PHY_EEE_EN_25GBASE_KR BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

842

#define IXGBE_ACI_PHY_EEE_EN_10BASE_T BIT(11)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

847

#define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

848

#define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

849

#define IXGBE_ACI_PHY_FEC_25G_RS_528_REQ BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

850

#define IXGBE_ACI_PHY_FEC_25G_KR_REQ BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

851

#define IXGBE_ACI_PHY_FEC_25G_RS_544_REQ BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

852

#define IXGBE_ACI_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

853

#define IXGBE_ACI_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

856

#define IXGBE_ACI_MOD_ENFORCE_STRICT_MODE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

863

#define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

864

#define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

865

#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

866

#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

867

#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

868

#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

902

#define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

903

#define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

904

#define IXGBE_ACI_PHY_ENA_LOW_POWER BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

905

#define IXGBE_ACI_PHY_ENA_LINK BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

906

#define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

907

#define IXGBE_ACI_PHY_ENA_LESM BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

908

#define IXGBE_ACI_PHY_ENA_AUTO_FEC BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

924

#define IXGBE_ACI_RESTART_AN_LINK_RESTART BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

925

#define IXGBE_ACI_RESTART_AN_LINK_ENABLE BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

952

#define IXGBE_ACI_LINK_TOPO_CONFLICT BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

953

#define IXGBE_ACI_LINK_MEDIA_CONFLICT BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

954

#define IXGBE_ACI_LINK_TOPO_CORRUPT BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

955

#define IXGBE_ACI_LINK_TOPO_UNREACH_PRT BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

956

#define IXGBE_ACI_LINK_TOPO_UNDRUTIL_PRT BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

957

#define IXGBE_ACI_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

958

#define IXGBE_ACI_LINK_TOPO_UNSUPP_MEDIA BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

960

#define IXGBE_ACI_LINK_CFG_ERR BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

961

#define IXGBE_ACI_LINK_CFG_COMPLETED BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

962

#define IXGBE_ACI_LINK_ACT_PORT_OPT_INVAL BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

963

#define IXGBE_ACI_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

964

#define IXGBE_ACI_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

965

#define IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

966

#define IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

967

#define IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

969

#define IXGBE_ACI_LINK_UP BIT(0) /* Link Status */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

970

#define IXGBE_ACI_LINK_FAULT BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

971

#define IXGBE_ACI_LINK_FAULT_TX BIT(2)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

972

#define IXGBE_ACI_LINK_FAULT_RX BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

973

#define IXGBE_ACI_LINK_FAULT_REMOTE BIT(4)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

974

#define IXGBE_ACI_LINK_UP_PORT BIT(5) /* External Port Link Status */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

975

#define IXGBE_ACI_MEDIA_AVAILABLE BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

976

#define IXGBE_ACI_SIGNAL_DETECT BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

978

#define IXGBE_ACI_AN_COMPLETED BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

979

#define IXGBE_ACI_LP_AN_ABILITY BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

980

#define IXGBE_ACI_PD_FAULT BIT(2) /* Parallel Detection Fault */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

981

#define IXGBE_ACI_FEC_EN BIT(3)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

982

#define IXGBE_ACI_PHY_LOW_POWER BIT(4) /* Low Power State */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

983

#define IXGBE_ACI_LINK_PAUSE_TX BIT(5)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

984

#define IXGBE_ACI_LINK_PAUSE_RX BIT(6)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

985

#define IXGBE_ACI_QUALIFIED_MODULE BIT(7)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

987

#define IXGBE_ACI_LINK_PHY_TEMP_ALARM BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

988

#define IXGBE_ACI_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

996

#define IXGBE_ACI_LINK_LB_PHY_LCL BIT(0)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

997

#define IXGBE_ACI_LINK_LB_PHY_RMT BIT(1)

usr/src/uts/common/io/ixgbe/core/ixgbe_type_e610.h

998

#define IXGBE_ACI_LINK_LB_MAC_LCL BIT(2)

usr/src/uts/common/io/rtw/max2820reg.h

103

#define MAX2820_ENABLE_PLL BIT(2)

usr/src/uts/common/io/rtw/max2820reg.h

108

#define MAX2820_ENABLE_VCO BIT(1)

usr/src/uts/common/io/rtw/max2820reg.h

109

#define MAX2820_ENABLE_RSVD0 BIT(0) /* reserved */

usr/src/uts/common/io/rtw/max2820reg.h

121

#define MAX2820_SYNTH_ICP BIT(6)

usr/src/uts/common/io/rtw/max2820reg.h

169

#define MAX2820_RECEIVE_SF BIT(3)

usr/src/uts/common/io/rtw/max2820reg.h

58

#define MAX2820_ENABLE_RSVD1 BIT(11) /* reserved */

usr/src/uts/common/io/rtw/max2820reg.h

63

#define MAX2820_ENABLE_PAB BIT(10)

usr/src/uts/common/io/rtw/max2820reg.h

68

#define MAX2820_ENABLE_TXFLT BIT(9)

usr/src/uts/common/io/rtw/max2820reg.h

73

#define MAX2820_ENABLE_TXUVD BIT(8)

usr/src/uts/common/io/rtw/max2820reg.h

78

#define MAX2820_ENABLE_DET BIT(7)

usr/src/uts/common/io/rtw/max2820reg.h

83

#define MAX2820_ENABLE_RXDFA BIT(6)

usr/src/uts/common/io/rtw/max2820reg.h

88

#define MAX2820_ENABLE_RXLNA BIT(5)

usr/src/uts/common/io/rtw/max2820reg.h

93

#define MAX2820_ENABLE_AT BIT(4)

usr/src/uts/common/io/rtw/max2820reg.h

98

#define MAX2820_ENABLE_CP BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

1004

#define RTW_FFER_INTR BIT(15) /* TBD */

usr/src/uts/common/io/rtw/rtwreg.h

1005

#define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */

usr/src/uts/common/io/rtw/rtwreg.h

1047

#define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */

usr/src/uts/common/io/rtw/rtwreg.h

1048

#define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */

usr/src/uts/common/io/rtw/rtwreg.h

1078

#define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */

usr/src/uts/common/io/rtw/rtwreg.h

1079

#define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */

usr/src/uts/common/io/rtw/rtwreg.h

1080

#define RTW_TXCTL0_FS BIT(29) /* first segment */

usr/src/uts/common/io/rtw/rtwreg.h

1081

#define RTW_TXCTL0_LS BIT(28) /* last segment */

usr/src/uts/common/io/rtw/rtwreg.h

1089

#define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */

usr/src/uts/common/io/rtw/rtwreg.h

1097

#define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */

usr/src/uts/common/io/rtw/rtwreg.h

1098

#define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */

usr/src/uts/common/io/rtw/rtwreg.h

1102

#define RTW_TXCTL0_SPLCP BIT(16)

usr/src/uts/common/io/rtw/rtwreg.h

1115

#define RTW_TXSTAT_TOK BIT(15)

usr/src/uts/common/io/rtw/rtwreg.h

1122

#define RTW_TXCTL1_LENGEXT BIT(31)

usr/src/uts/common/io/rtw/rtwreg.h

1146

#define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */

usr/src/uts/common/io/rtw/rtwreg.h

1147

#define RTW_RXCTL_EOR BIT(30) /* end of ring */

usr/src/uts/common/io/rtw/rtwreg.h

1148

#define RTW_RXCTL_FS BIT(29) /* first segment */

usr/src/uts/common/io/rtw/rtwreg.h

1149

#define RTW_RXCTL_LS BIT(28) /* last segment */

usr/src/uts/common/io/rtw/rtwreg.h

1157

#define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */

usr/src/uts/common/io/rtw/rtwreg.h

1161

#define RTW_RXSTAT_BOVF BIT(26)

usr/src/uts/common/io/rtw/rtwreg.h

1165

#define RTW_RXSTAT_SPLCP BIT(25)

usr/src/uts/common/io/rtw/rtwreg.h

1166

#define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */

usr/src/uts/common/io/rtw/rtwreg.h

1172

#define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */

usr/src/uts/common/io/rtw/rtwreg.h

1173

#define RTW_RXSTAT_MAR BIT(18) /* is multicast */

usr/src/uts/common/io/rtw/rtwreg.h

1174

#define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */

usr/src/uts/common/io/rtw/rtwreg.h

1175

#define RTW_RXSTAT_BAR BIT(16) /* is broadcast */

usr/src/uts/common/io/rtw/rtwreg.h

1180

#define RTW_RXSTAT_RES BIT(15)

usr/src/uts/common/io/rtw/rtwreg.h

1181

#define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */

usr/src/uts/common/io/rtw/rtwreg.h

1185

#define RTW_RXSTAT_CRC16 BIT(14)

usr/src/uts/common/io/rtw/rtwreg.h

1186

#define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */

usr/src/uts/common/io/rtw/rtwreg.h

1187

#define RTW_RXSTAT_ICV BIT(12) /* ICV error */

usr/src/uts/common/io/rtw/rtwreg.h

1216

#define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */

usr/src/uts/common/io/rtw/rtwreg.h

136

#define RTW_BRSR_BPLCP BIT(8)

usr/src/uts/common/io/rtw/rtwreg.h

146

#define RTW_BRSR_MBR8181_1MBPS BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

147

#define RTW_BRSR_MBR8181_2MBPS BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

148

#define RTW_BRSR_MBR8181_5MBPS BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

149

#define RTW_BRSR_MBR8181_11MBPS BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

170

#define RTW_CR_RST BIT(4)

usr/src/uts/common/io/rtw/rtwreg.h

177

#define RTW_CR_RE BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

184

#define RTW_CR_TE BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

190

#define RTW_CR_MULRW BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

195

#define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */

usr/src/uts/common/io/rtw/rtwreg.h

199

#define RTW_INTR_TIMEOUT BIT(14)

usr/src/uts/common/io/rtw/rtwreg.h

205

#define RTW_INTR_BCNINT BIT(13)

usr/src/uts/common/io/rtw/rtwreg.h

211

#define RTW_INTR_ATIMINT BIT(12)

usr/src/uts/common/io/rtw/rtwreg.h

217

#define RTW_INTR_TBDER BIT(11)

usr/src/uts/common/io/rtw/rtwreg.h

218

#define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */

usr/src/uts/common/io/rtw/rtwreg.h

223

#define RTW_INTR_THPDER BIT(9)

usr/src/uts/common/io/rtw/rtwreg.h

224

#define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */

usr/src/uts/common/io/rtw/rtwreg.h

229

#define RTW_INTR_TNPDER BIT(7)

usr/src/uts/common/io/rtw/rtwreg.h

230

#define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */

usr/src/uts/common/io/rtw/rtwreg.h

235

#define RTW_INTR_RXFOVW BIT(5)

usr/src/uts/common/io/rtw/rtwreg.h

236

#define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */

usr/src/uts/common/io/rtw/rtwreg.h

241

#define RTW_INTR_TLPDER BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

242

#define RTW_INTR_TLPDOK BIT(2) /* Tx Low Priority Descriptor OK */

usr/src/uts/common/io/rtw/rtwreg.h

243

#define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */

usr/src/uts/common/io/rtw/rtwreg.h

244

#define RTW_INTR_ROK BIT(0) /* Rx OK */

usr/src/uts/common/io/rtw/rtwreg.h

258

#define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */

usr/src/uts/common/io/rtw/rtwreg.h

263

#define RTW_TCR_SWSEQ BIT(30)

usr/src/uts/common/io/rtw/rtwreg.h

275

#define RTW_TCR_SAT BIT(24)

usr/src/uts/common/io/rtw/rtwreg.h

287

#define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */

usr/src/uts/common/io/rtw/rtwreg.h

292

#define RTW_TCR_ICV BIT(19)

usr/src/uts/common/io/rtw/rtwreg.h

310

#define RTW_TCR_CRC BIT(16)

usr/src/uts/common/io/rtw/rtwreg.h

318

#define RTW_RCR_ONLYERLPKT BIT(31)

usr/src/uts/common/io/rtw/rtwreg.h

319

#define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */

usr/src/uts/common/io/rtw/rtwreg.h

320

#define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */

usr/src/uts/common/io/rtw/rtwreg.h

321

#define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */

usr/src/uts/common/io/rtw/rtwreg.h

327

#define RTW_RCR_CBSSID BIT(23)

usr/src/uts/common/io/rtw/rtwreg.h

328

#define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */

usr/src/uts/common/io/rtw/rtwreg.h

333

#define RTW_RCR_ADD3 BIT(21)

usr/src/uts/common/io/rtw/rtwreg.h

334

#define RTW_RCR_AMF BIT(20) /* accept management frames */

usr/src/uts/common/io/rtw/rtwreg.h

335

#define RTW_RCR_ACF BIT(19) /* accept control frames */

usr/src/uts/common/io/rtw/rtwreg.h

336

#define RTW_RCR_ADF BIT(18) /* accept data frames */

usr/src/uts/common/io/rtw/rtwreg.h

349

#define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */

usr/src/uts/common/io/rtw/rtwreg.h

367

#define RTW_RCR_9356SEL BIT(6)

usr/src/uts/common/io/rtw/rtwreg.h

369

#define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */

usr/src/uts/common/io/rtw/rtwreg.h

370

#define RTW_RCR_AB BIT(3) /* accept broadcast frames */

usr/src/uts/common/io/rtw/rtwreg.h

371

#define RTW_RCR_AM BIT(2) /* accept multicast frames */

usr/src/uts/common/io/rtw/rtwreg.h

375

#define RTW_RCR_APM BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

376

#define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */

usr/src/uts/common/io/rtw/rtwreg.h

450

#define RTW_9346CR_EECS BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

451

#define RTW_9346CR_EESK BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

452

#define RTW_9346CR_EEDI BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

453

#define RTW_9346CR_EEDO BIT(0) /* read-only */

usr/src/uts/common/io/rtw/rtwreg.h

459

#define RTW_CONFIG0_WEP40 BIT(7)

usr/src/uts/common/io/rtw/rtwreg.h

463

#define RTW_CONFIG0_WEP104 BIT(6)

usr/src/uts/common/io/rtw/rtwreg.h

469

#define RTW_CONFIG0_LEDGPOEN BIT(4)

usr/src/uts/common/io/rtw/rtwreg.h

473

#define RTW_CONFIG0_AUXPWR BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

516

#define RTW_CONFIG1_LWACT BIT(4)

usr/src/uts/common/io/rtw/rtwreg.h

518

#define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */

usr/src/uts/common/io/rtw/rtwreg.h

519

#define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */

usr/src/uts/common/io/rtw/rtwreg.h

524

#define RTW_CONFIG1_VPD BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

525

#define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */

usr/src/uts/common/io/rtw/rtwreg.h

532

#define RTW_CONFIG2_LCK BIT(7)

usr/src/uts/common/io/rtw/rtwreg.h

533

#define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */

usr/src/uts/common/io/rtw/rtwreg.h

537

#define RTW_CONFIG2_DPS BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

538

#define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */

usr/src/uts/common/io/rtw/rtwreg.h

54

#define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))

usr/src/uts/common/io/rtw/rtwreg.h

554

#define RTW_ANAPARM_TXDACOFF BIT(27)

usr/src/uts/common/io/rtw/rtwreg.h

641

#define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */

usr/src/uts/common/io/rtw/rtwreg.h

646

#define RTW_CONFIG3_PARMEN BIT(6)

usr/src/uts/common/io/rtw/rtwreg.h

651

#define RTW_CONFIG3_MAGIC BIT(5)

usr/src/uts/common/io/rtw/rtwreg.h

656

#define RTW_CONFIG3_CARDBEN BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

660

#define RTW_CONFIG3_CLKRUNEN BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

664

#define RTW_CONFIG3_FUNCREGEN BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

668

#define RTW_CONFIG3_FBTBEN BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

677

#define RTW_CONFIG4_VCOPDN BIT(7)

usr/src/uts/common/io/rtw/rtwreg.h

688

#define RTW_CONFIG4_PWROFF BIT(6)

usr/src/uts/common/io/rtw/rtwreg.h

695

#define RTW_CONFIG4_PWRMGT BIT(5)

usr/src/uts/common/io/rtw/rtwreg.h

705

#define RTW_CONFIG4_LWPME BIT(4)

usr/src/uts/common/io/rtw/rtwreg.h

709

#define RTW_CONFIG4_LWPTN BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

721

#define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */

usr/src/uts/common/io/rtw/rtwreg.h

722

#define RTW_PSR_GPI BIT(6) /* Status of pin 64. */

usr/src/uts/common/io/rtw/rtwreg.h

726

#define RTW_PSR_LEDGPO1 BIT(5)

usr/src/uts/common/io/rtw/rtwreg.h

730

#define RTW_PSR_LEDGPO0 BIT(4)

usr/src/uts/common/io/rtw/rtwreg.h

731

#define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */

usr/src/uts/common/io/rtw/rtwreg.h

732

#define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */

usr/src/uts/common/io/rtw/rtwreg.h

742

#define RTW_SCR_TXSECON BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

747

#define RTW_SCR_RXSECON BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

777

#define RTW_PHYDELAY_REVC_MAGIC BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

793

#define RTW_BB_WREN BIT(7) /* write enable */

usr/src/uts/common/io/rtw/rtwreg.h

804

#define RTW_PHYCFG_MAC_POLL BIT(31)

usr/src/uts/common/io/rtw/rtwreg.h

809

#define RTW_PHYCFG_HST BIT(30)

usr/src/uts/common/io/rtw/rtwreg.h

820

#define RTW_PHYCFG_HST_EN BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

821

#define RTW_PHYCFG_HST_CLK BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

822

#define RTW_PHYCFG_HST_DATA BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

877

#define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */

usr/src/uts/common/io/rtw/rtwreg.h

878

#define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */

usr/src/uts/common/io/rtw/rtwreg.h

883

#define RTW_CONFIG5_CALON BIT(5)

usr/src/uts/common/io/rtw/rtwreg.h

884

#define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */

usr/src/uts/common/io/rtw/rtwreg.h

888

#define RTW_CONFIG5_LANWAKE BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

895

#define RTW_CONFIG5_PMESTS BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

905

#define RTW_TPPOLL_BQ BIT(7)

usr/src/uts/common/io/rtw/rtwreg.h

910

#define RTW_TPPOLL_HPQ BIT(6)

usr/src/uts/common/io/rtw/rtwreg.h

919

#define RTW_TPPOLL_NPQ BIT(5)

usr/src/uts/common/io/rtw/rtwreg.h

924

#define RTW_TPPOLL_LPQ BIT(4)

usr/src/uts/common/io/rtw/rtwreg.h

929

#define RTW_TPPOLL_SBQ BIT(3)

usr/src/uts/common/io/rtw/rtwreg.h

933

#define RTW_TPPOLL_SHPQ BIT(2)

usr/src/uts/common/io/rtw/rtwreg.h

938

#define RTW_TPPOLL_SNPQ BIT(1)

usr/src/uts/common/io/rtw/rtwreg.h

942

#define RTW_TPPOLL_SLPQ BIT(0)

usr/src/uts/common/io/rtw/rtwreg.h

980

#define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */

usr/src/uts/common/io/rtw/rtwreg.h

981

#define RTW_FER_GWAKE BIT(4) /* General Wakeup */

usr/src/uts/common/io/rtw/rtwreg.h

987

#define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */

usr/src/uts/common/io/rtw/rtwreg.h

988

#define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */

usr/src/uts/common/io/rtw/rtwreg.h

989

#define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */

usr/src/uts/common/io/rtw/rtwreg.h

996

#define RTW_FPSR_INTR BIT(15) /* TBD */

usr/src/uts/common/io/rtw/rtwreg.h

997

#define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */

usr/src/uts/common/io/rtw/sa2400reg.h

111

#define SA2400_SYNC_ZERO BIT(2) /* always 0 */

usr/src/uts/common/io/rtw/sa2400reg.h

120

#define SA2400_SYND_TPHPSU BIT(16)

usr/src/uts/common/io/rtw/sa2400reg.h

125

#define SA2400_SYND_TPSU BIT(15)

usr/src/uts/common/io/rtw/sa2400reg.h

136

#define SA2400_OPMODE_ADC BIT(19)

usr/src/uts/common/io/rtw/sa2400reg.h

141

#define SA2400_OPMODE_FTERR BIT(18)

usr/src/uts/common/io/rtw/sa2400reg.h

151

#define SA2400_OPMODE_V2P5 BIT(14)

usr/src/uts/common/io/rtw/sa2400reg.h

152

#define SA2400_OPMODE_I1M BIT(13) /* external reference current ... */

usr/src/uts/common/io/rtw/sa2400reg.h

153

#define SA2400_OPMODE_I0P3 BIT(12) /* external reference current ... */

usr/src/uts/common/io/rtw/sa2400reg.h

159

#define SA2400_OPMODE_IN22 BIT(10)

usr/src/uts/common/io/rtw/sa2400reg.h

160

#define SA2400_OPMODE_CLK BIT(9) /* reference clock output on */

usr/src/uts/common/io/rtw/sa2400reg.h

161

#define SA2400_OPMODE_XO BIT(8) /* xtal oscillator on */

usr/src/uts/common/io/rtw/sa2400reg.h

162

#define SA2400_OPMODE_DIGIN BIT(7) /* use digital Tx inputs (FIRDAC) */

usr/src/uts/common/io/rtw/sa2400reg.h

168

#define SA2400_OPMODE_RXLV BIT(6)

usr/src/uts/common/io/rtw/sa2400reg.h

173

#define SA2400_OPMODE_VEO BIT(5)

usr/src/uts/common/io/rtw/sa2400reg.h

174

#define SA2400_OPMODE_VEI BIT(4) /* use external vco input (vcoextin) */

usr/src/uts/common/io/rtw/sa2400reg.h

196

#define SA2400_AGC_TARGETSIGN BIT(23)

usr/src/uts/common/io/rtw/sa2400reg.h

232

#define SA2400_MANRX_AHSN BIT(23)

usr/src/uts/common/io/rtw/sa2400reg.h

241

#define SA2400_MANRX_RXOSQON BIT(22) /* Rx Q-channel correction. */

usr/src/uts/common/io/rtw/sa2400reg.h

242

#define SA2400_MANRX_RXOSQSIGN BIT(21)

usr/src/uts/common/io/rtw/sa2400reg.h

245

#define SA2400_MANRX_RXOSION BIT(17) /* Rx I-channel correction. */

usr/src/uts/common/io/rtw/sa2400reg.h

246

#define SA2400_MANRX_RXOSISIGN BIT(16)

usr/src/uts/common/io/rtw/sa2400reg.h

252

#define SA2400_MANRX_TEN BIT(12)

usr/src/uts/common/io/rtw/sa2400reg.h

273

#define SA2400_TX_TXOSQON BIT(19)

usr/src/uts/common/io/rtw/sa2400reg.h

274

#define SA2400_TX_TXOSQSIGN BIT(18)

usr/src/uts/common/io/rtw/sa2400reg.h

276

#define SA2400_TX_TXOSION BIT(14)

usr/src/uts/common/io/rtw/sa2400reg.h

277

#define SA2400_TX_TXOSISIGN BIT(13)

usr/src/uts/common/io/rtw/sa2400reg.h

308

#define SA2400_VCO_VCERR BIT(4)

usr/src/uts/common/io/rtw/sa2400reg.h

46

#define SA2400_TWI_WREN BIT(7) /* enable write */

usr/src/uts/common/io/rtw/sa2400reg.h

58

#define SA2400_SYNA_FM BIT(21)

usr/src/uts/common/io/rtw/sa2400reg.h

89

#define SA2400_SYNB_ON BIT(9)

usr/src/uts/common/io/rtw/sa2400reg.h

90

#define SA2400_SYNB_ONE BIT(8) /* always 1 */

usr/src/uts/common/io/rtw/si4136reg.h

72

#define SI4126_MAIN_XINDIV2 BIT(6) /* 1: divide crystal input (XIN) by 2 */

usr/src/uts/common/io/rtw/si4136reg.h

73

#define SI4126_MAIN_LPWR BIT(5) /* 1: low-power mode */

usr/src/uts/common/io/rtw/si4136reg.h

79

#define SI4126_MAIN_AUTOPDB BIT(3)

usr/src/uts/common/io/rtw/si4136reg.h

86

#define SI4126_POWER_PDIB BIT(1) /* 1: IF synthesizer on */

usr/src/uts/common/io/rtw/si4136reg.h

87

#define SI4126_POWER_PDRB BIT(0) /* 1: RF synthesizer on */

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

122

#define XFR_MODE_DMA_EN BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

123

#define XFR_MODE_COUNT BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

124

#define XFR_MODE_AUTO_CMD12 BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

125

#define XFR_MODE_READ BIT(4) /* 1 = read, 0 = write */

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

126

#define XFR_MODE_MULTI BIT(5) /* 1 = multi, 0 = single */

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

129

#define COMMAND_CRC_CHECK_EN BIT(3)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

130

#define COMMAND_INDEX_CHECK_EN BIT(4)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

131

#define COMMAND_DATA_PRESENT BIT(5)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

144

#define PRS_CMD_INHIBIT BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

145

#define PRS_DAT_INHIBIT BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

146

#define PRS_DAT_ACTIVE BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

147

#define PRS_WRITE_ACTIVE BIT(8)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

148

#define PRS_READ_ACTIVE BIT(9)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

149

#define PRS_BUF_WR_EN BIT(10)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

150

#define PRS_BUF_RD_EN BIT(11)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

151

#define PRS_CARD_INSERTED BIT(16)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

152

#define PRS_CARD_STABLE BIT(17)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

153

#define PRS_CARD_DETECT BIT(18)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

154

#define PRS_WRITE_ENABLE BIT(19)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

155

#define PRS_DAT0_SIG BIT(20)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

156

#define PRS_DAT1_SIG BIT(21)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

157

#define PRS_DAT2_SIG BIT(22)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

158

#define PRS_DAT3_SIG BIT(23)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

166

#define HOST_CONTROL_LED_ON BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

167

#define HOST_CONTROL_DATA_WIDTH BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

168

#define HOST_CONTROL_HIGH_SPEED_EN BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

173

#define HOST_CONTROL_CARD_DETECT_TEST BIT(6)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

174

#define HOST_CONTROL_CARD_DETECT_SEL BIT(7)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

177

#define POWER_CONTROL_BUS_POWER BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

183

#define BLOCK_GAP_CONTROL_STOP BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

184

#define BLOCK_GAP_CONTROL_CONTINUE BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

185

#define BLOCK_GAP_CONTROL_READ_WAIT BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

186

#define BLOCK_GAP_CONTROL_INTERRUPT BIT(3)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

189

#define WAKEUP_CONTROL_INTERRUPT BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

190

#define WAKEUP_CONTROL_INSERT BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

191

#define WAKEUP_CONTROL_REMOVE BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

194

#define CLOCK_CONTROL_INT_CLOCK_EN BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

195

#define CLOCK_CONTROL_INT_CLOCK_STABLE BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

196

#define CLOCK_CONTROL_SD_CLOCK_EN BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

206

#define SOFT_RESET_ALL BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

207

#define SOFT_RESET_CMD BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

208

#define SOFT_RESET_DAT BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

211

#define INT_CMD BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

212

#define INT_XFR BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

213

#define INT_BG BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

214

#define INT_DMA BIT(3)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

215

#define INT_WR BIT(4)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

216

#define INT_RD BIT(5)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

217

#define INT_INS BIT(6)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

218

#define INT_REM BIT(7)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

219

#define INT_CARD BIT(8)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

220

#define INT_ERR BIT(15)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

230

#define ERR_ADMA BIT(9)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

231

#define ERR_ACMD12 BIT(8)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

232

#define ERR_CURRENT BIT(7)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

233

#define ERR_DAT_END BIT(6)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

234

#define ERR_DAT_CRC BIT(5)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

235

#define ERR_DAT_TMO BIT(4)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

236

#define ERR_CMD_IDX BIT(3)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

237

#define ERR_CMD_END BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

238

#define ERR_CMD_CRC BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

239

#define ERR_CMD_TMO BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

250

#define ACMD12_ERROR_NOT_EXECUTED BIT(0)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

251

#define ACMD12_ERROR_TIMEOUT BIT(1)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

252

#define ACMD12_ERROR_CRC BIT(2)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

253

#define ACMD12_ERROR_END_BIT BIT(3)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

254

#define ACMD12_ERROR_INDEX BIT(4)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

255

#define ACMD12_ERROR_NOT_ISSUED BIT(7)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

260

#define CAPAB_TIMEOUT_UNITS BIT(7) /* 1 == MHz, 0 = kHz */

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

267

#define CAPAB_ADMA2 BIT(19)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

268

#define CAPAB_ADMA1 BIT(20)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

269

#define CAPAB_HIGH_SPEED BIT(21)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

270

#define CAPAB_SDMA BIT(22)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

271

#define CAPAB_SUSPEND BIT(23)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

272

#define CAPAB_33V BIT(24)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

273

#define CAPAB_30V BIT(25)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

274

#define CAPAB_18V BIT(26)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

276

#define CAPAB_64BIT BIT(28)

usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.h

298

#define ADMA_ERROR_LEN_MISMATCH BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

100

#define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

110

#define XGE_HAL_TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

111

#define XGE_HAL_TXD_TX_CKO_IPV4_EN BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

112

#define XGE_HAL_TXD_TX_CKO_TCP_EN BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

113

#define XGE_HAL_TXD_TX_CKO_UDP_EN BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

114

#define XGE_HAL_TXD_VLAN_ENABLE BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

117

#define XGE_HAL_TXD_INT_TYPE_PER_LIST BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

118

#define XGE_HAL_TXD_INT_TYPE_UTILZ BIT(46)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

58

#define XGE_HAL_TX_FIFO_FIRST_LIST BIT(14)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

59

#define XGE_HAL_TX_FIFO_LAST_LIST BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

61

#define XGE_HAL_TX_FIFO_SPECIAL_FUNC BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

94

#define XGE_HAL_TXD_LIST_OWN_XENA BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

95

#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

98

#define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23))

usr/src/uts/common/io/xge/hal/include/xgehal-fifo.h

99

#define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

100

#define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

101

#define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1028

#define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1030

#define XGE_HAL_MC_INT_MASK_MC_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1033

#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1034

#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1035

#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1036

#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1037

#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1038

#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1039

#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

104

#define XGE_HAL_ADAPTER_CNTL_EN BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1040

#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1041

#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1042

#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1043

#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1044

#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1045

#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1046

#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1047

#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1048

#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1049

#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

105

#define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1050

#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1051

#define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1052

#define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

106

#define XGE_HAL_ADAPTER_LED_ON BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1071

#define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1072

#define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

108

#define XGE_HAL_ADAPTER_WAIT_INT BIT(48)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1085

#define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1086

#define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1087

#define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1088

#define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1089

#define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

109

#define XGE_HAL_ADAPTER_ECC_EN BIT(55)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

112

#define XGE_HAL_SERR_SOURCE_PIC BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

113

#define XGE_HAL_SERR_SOURCE_TXDMA BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1138

#define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1139

#define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

114

#define XGE_HAL_SERR_SOURCE_RXDMA BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1141

#define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1142

#define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1145

#define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1146

#define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1147

#define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1148

#define XGE_HAL_TXGXS_TX_SM_ERR BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

115

#define XGE_HAL_SERR_SOURCE_MAC BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1153

#define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

1154

#define XGE_HAL_RXGXS_RX_SM_ERR BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

116

#define XGE_HAL_SERR_SOURCE_MC BIT(4)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

117

#define XGE_HAL_SERR_SOURCE_XGXS BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

127

#define XGE_HAL_PCI_32_BIT BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

142

#define XGE_HAL_PIC_INT_TX BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

143

#define XGE_HAL_PIC_INT_FLSH BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

144

#define XGE_HAL_PIC_INT_MDIO BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

145

#define XGE_HAL_PIC_INT_IIC BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

146

#define XGE_HAL_PIC_INT_MISC BIT(4)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

147

#define XGE_HAL_PIC_INT_RX BIT(32)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

150

#define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

152

#define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

153

#define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

154

#define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

155

#define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

156

#define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

157

#define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

158

#define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

159

#define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

160

#define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

161

#define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

162

#define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

163

#define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

164

#define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

172

#define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

173

#define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

174

#define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

180

#define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

181

#define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

186

#define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

187

#define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

188

#define XGE_HAL_MDIO_INT_REG_LASI BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

193

#define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

194

#define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

195

#define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

196

#define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

197

#define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

203

#define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

204

#define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

205

#define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

218

#define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

222

#define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

227

#define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

228

#define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

232

#define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

233

#define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

234

#define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

235

#define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

236

#define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

237

#define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

238

#define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

239

#define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

240

#define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

241

#define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

242

#define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

243

#define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

244

#define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

245

#define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

246

#define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

247

#define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

248

#define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

249

#define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

250

#define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

251

#define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

252

#define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

253

#define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

254

#define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

255

#define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

261

#define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

262

#define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

270

#define XGE_HAL_TXREQTO_EN BIT(63)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

274

#define XGE_HAL_STATREQTO_EN BIT(63)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

282

#define XGE_HAL_XMSI_EN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

283

#define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

287

#define XGE_HAL_XMSI_WR_RDN BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

288

#define XGE_HAL_XMSI_STROBE BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

308

#define XGE_HAL_STAT_CFG_STAT_EN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

309

#define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

310

#define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

311

#define XGE_HAL_STAT_CFG_STAT_RO BIT(9)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

354

#define XGE_HAL_I2C_CONTROL_READ BIT(24)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

355

#define XGE_HAL_I2C_CONTROL_NACK BIT(25)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

364

#define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

365

#define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

369

#define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

38

#define XGE_HAL_GEN_INTR_TXPIC BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

39

#define XGE_HAL_GEN_INTR_TXDMA BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

40

#define XGE_HAL_GEN_INTR_TXMAC BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

41

#define XGE_HAL_GEN_INTR_TXXGXS BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

42

#define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

43

#define XGE_HAL_GEN_INTR_RXPIC BIT(32)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

433

#define XGE_HAL_TXDMA_PFC_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

434

#define XGE_HAL_TXDMA_TDA_INT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

435

#define XGE_HAL_TXDMA_PCC_INT BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

436

#define XGE_HAL_TXDMA_TTI_INT BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

437

#define XGE_HAL_TXDMA_LSO_INT BIT(4)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

438

#define XGE_HAL_TXDMA_TPA_INT BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

439

#define XGE_HAL_TXDMA_SM_INT BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

44

#define XGE_HAL_GEN_INTR_RXDMA BIT(33)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

441

#define XGE_HAL_PFC_ECC_SG_ERR BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

442

#define XGE_HAL_PFC_ECC_DB_ERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

443

#define XGE_HAL_PFC_SM_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

444

#define XGE_HAL_PFC_MISC_0_ERR BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

445

#define XGE_HAL_PFC_MISC_1_ERR BIT(32)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

446

#define XGE_HAL_PFC_PCIX_ERR BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

45

#define XGE_HAL_GEN_INTR_RXMAC BIT(34)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

453

#define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

454

#define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

455

#define XGE_HAL_TDA_PCIX_ERR BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

46

#define XGE_HAL_GEN_INTR_MC BIT(35)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

468

#define XGE_HAL_PCC_6_COF_OV_ERR BIT(56)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

469

#define XGE_HAL_PCC_7_COF_OV_ERR BIT(57)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

47

#define XGE_HAL_GEN_INTR_RXXGXS BIT(36)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

470

#define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

471

#define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

476

#define XGE_HAL_TTI_ECC_SG_ERR BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

477

#define XGE_HAL_TTI_ECC_DB_ERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

478

#define XGE_HAL_TTI_SM_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

48

#define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

483

#define XGE_HAL_LSO6_SEND_OFLOW BIT(12)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

484

#define XGE_HAL_LSO7_SEND_OFLOW BIT(13)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

485

#define XGE_HAL_LSO6_ABORT BIT(14)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

486

#define XGE_HAL_LSO7_ABORT BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

487

#define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

488

#define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

493

#define XGE_HAL_TPA_TX_FRM_DROP BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

494

#define XGE_HAL_TPA_SM_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

499

#define XGE_HAL_SM_SM_ERR_ALARM BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

512

#define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

552

#define XGE_HAL_TTI_CMD_MEM_WE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

553

#define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

554

#define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

560

#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

561

#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

574

#define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

575

#define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

576

#define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

577

#define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

598

#define XGE_HAL_RXDMA_RC_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

599

#define XGE_HAL_RXDMA_RPA_INT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

600

#define XGE_HAL_RXDMA_RDA_INT BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

601

#define XGE_HAL_RXDMA_RTI_INT BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

604

#define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

605

#define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

606

#define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

607

#define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

612

#define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

613

#define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

614

#define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

615

#define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

616

#define XGE_HAL_RDA_MISC_ERR BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

617

#define XGE_HAL_RDA_PCIX_ERR BIT(55)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

618

#define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

625

#define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

626

#define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

628

#define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

644

#define XGE_HAL_RPA_ECC_SG_ERR BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

645

#define XGE_HAL_RPA_ECC_DB_ERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

646

#define XGE_HAL_RPA_FLUSH_REQUEST BIT(22)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

647

#define XGE_HAL_RPA_SM_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

648

#define XGE_HAL_RPA_CREDIT_ERR BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

653

#define XGE_HAL_RTI_ECC_SG_ERR BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

654

#define XGE_HAL_RTI_ECC_DB_ERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

655

#define XGE_HAL_RTI_SM_ERR_ALARM BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

691

#define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

692

#define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15))

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

698

#define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

699

#define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

700

#define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

704

#define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

705

#define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

706

#define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

707

#define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

708

#define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

709

#define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

710

#define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

711

#define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

712

#define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

713

#define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

714

#define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

715

#define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

716

#define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

717

#define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

718

#define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

719

#define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

723

#define XGE_HAL_RTI_CMD_MEM_WE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

724

#define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

725

#define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

726

#define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

731

#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

732

#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

744

#define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

745

#define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

746

#define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

765

#define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

766

#define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

769

#define XGE_HAL_TMAC_ECC_DB_ERR BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

770

#define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

771

#define XGE_HAL_TMAC_TX_CRI_ERR BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

772

#define XGE_HAL_TMAC_TX_SM_ERR BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

777

#define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

778

#define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

779

#define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

780

#define XGE_HAL_RMAC_ECC_DB_ERR BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

781

#define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

782

#define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

783

#define XGE_HAL_RMAC_RX_SM_ERR BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

790

#define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

791

#define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

792

#define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

793

#define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

794

#define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

795

#define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

796

#define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

797

#define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

798

#define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

799

#define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

800

#define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

810

#define XGE_HAL_RMAC_ERR_FCS BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

811

#define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

812

#define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

813

#define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

814

#define XGE_HAL_RMAC_ERR_RUNT BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

815

#define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

816

#define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

817

#define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

828

#define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

830

#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

831

#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

836

#define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

853

#define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

854

#define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

86

#define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

87

#define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

88

#define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

885

#define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

89

#define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

892

#define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

893

#define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

894

#define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

897

#define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

898

#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

899

#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

90

#define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

902

#define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

907

#define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

908

#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

909

#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

91

#define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

92

#define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

924

#define XGE_HAL_RTS_MAC_SECT0_EN BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

925

#define XGE_HAL_RTS_MAC_SECT1_EN BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

926

#define XGE_HAL_RTS_MAC_SECT2_EN BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

927

#define XGE_HAL_RTS_MAC_SECT3_EN BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

928

#define XGE_HAL_RTS_MAC_SECT4_EN BIT(4)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

929

#define XGE_HAL_RTS_MAC_SECT5_EN BIT(5)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

930

#define XGE_HAL_RTS_MAC_SECT6_EN BIT(6)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

931

#define XGE_HAL_RTS_MAC_SECT7_EN BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

936

#define XGE_HAL_RTS_RTH_EN BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

938

#define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

939

#define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

940

#define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

941

#define XGE_HAL_RTS_RTH_IPV4_EN BIT(23)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

942

#define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

943

#define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

944

#define XGE_HAL_RTS_RTH_IPV6_EN BIT(35)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

945

#define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

946

#define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

947

#define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

950

#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

951

#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

955

#define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

959

#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

974

#define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

98

#define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24)

usr/src/uts/common/io/xge/hal/include/xgehal-regs.h

99

#define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

212

(u8)((Control_1 & BIT(18))>>45)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

214

(u8)((Control_1 & BIT(19))>>44)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

58

#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

59

#define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

60

#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

72

#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

73

#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

74

#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

75

#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

76

#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30)

usr/src/uts/common/io/xge/hal/include/xgehal-ring.h

77

#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

547

#define XGE_HAL_TXPIC_INT_M BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

548

#define XGE_HAL_TXDMA_INT_M BIT(1)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

549

#define XGE_HAL_TXMAC_INT_M BIT(2)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

550

#define XGE_HAL_TXXGXS_INT_M BIT(3)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

551

#define XGE_HAL_TXTRAFFIC_INT_M BIT(8)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

552

#define XGE_HAL_PIC_RX_INT_M BIT(32)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

553

#define XGE_HAL_RXDMA_INT_M BIT(33)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

554

#define XGE_HAL_RXMAC_INT_M BIT(34)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

555

#define XGE_HAL_MC_INT_M BIT(35)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

556

#define XGE_HAL_RXXGXS_INT_M BIT(36)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

557

#define XGE_HAL_RXTRAFFIC_INT_M BIT(40)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

576

#define XGE_HAL_TXDMA_PFC_INT_M BIT(0)

usr/src/uts/common/io/xge/hal/include/xgehal-types.h

579

#define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

1560

val64 = BIT(7) | BIT(15);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

1567

vBIT(rnum,37,3) | BIT(63);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

1569

val64 = BIT(47);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

1571

val64 = BIT(7);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

1576

val64 = BIT(7) | BIT(15) | vBIT(pnum,24,8);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

1967

BIT(63); /* entry enable bit */

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

5956

if ((spdm_line_val & BIT(63))) {

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

6339

if (!(spdm_line_arr[7] & BIT(63))) {

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

6353

spdm_is_tcp = (u8)((spdm_line_arr[0] & BIT(59)) >> 4);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

6354

spdm_is_ipv4 = (u8)(spdm_line_arr[0] & BIT(63));

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

6411

spdm_line_arr[7] &= ~BIT(63);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

6463

val64 &= ~BIT(ring_qid);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c

6489

val64 &= ~BIT(fifo_qid);

usr/src/uts/common/io/xge/hal/xgehal/xgehal-fifo.c

428

part0 |= BIT(0); /* to enable the FIFO partition. */

usr/src/uts/common/io/xge/hal/xgehal/xgehal-ring.c

530

val64 |= (BIT(i) >> (j*8));

usr/src/uts/common/io/yge/yge.h

1001

#define RB_WP_T_ON BIT(6) /* Write Pointer Test On */

usr/src/uts/common/io/yge/yge.h

1002

#define RB_WP_T_OFF BIT(5) /* Write Pointer Test Off */

usr/src/uts/common/io/yge/yge.h

1003

#define RB_WP_INC BIT(4) /* Write Pointer Increment */

usr/src/uts/common/io/yge/yge.h

1004

#define RB_RP_T_ON BIT(2) /* Read Pointer Test On */

usr/src/uts/common/io/yge/yge.h

1005

#define RB_RP_T_OFF BIT(1) /* Read Pointer Test Off */

usr/src/uts/common/io/yge/yge.h

1006

#define RB_RP_INC BIT(0) /* Read Pointer Increment */

usr/src/uts/common/io/yge/yge.h

1009

#define RB_ENA_STFWD BIT(5) /* Enable Store & Forward */

usr/src/uts/common/io/yge/yge.h

1010

#define RB_DIS_STFWD BIT(4) /* Disable Store & Forward */

usr/src/uts/common/io/yge/yge.h

1011

#define RB_ENA_OP_MD BIT(3) /* Enable Operation Mode */

usr/src/uts/common/io/yge/yge.h

1012

#define RB_DIS_OP_MD BIT(2) /* Disable Operation Mode */

usr/src/uts/common/io/yge/yge.h

1013

#define RB_RST_CLR BIT(1) /* Clear RAM Buf STM Reset */

usr/src/uts/common/io/yge/yge.h

1014

#define RB_RST_SET BIT(0) /* Set RAM Buf STM Reset */

usr/src/uts/common/io/yge/yge.h

1059

#define WOL_CTL_LINK_CHG_OCC BIT(15)

usr/src/uts/common/io/yge/yge.h

1060

#define WOL_CTL_MAGIC_PKT_OCC BIT(14)

usr/src/uts/common/io/yge/yge.h

1061

#define WOL_CTL_PATTERN_OCC BIT(13)

usr/src/uts/common/io/yge/yge.h

1062

#define WOL_CTL_CLEAR_RESULT BIT(12)

usr/src/uts/common/io/yge/yge.h

1063

#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT(11)

usr/src/uts/common/io/yge/yge.h

1064

#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT(10)

usr/src/uts/common/io/yge/yge.h

1065

#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT(9)

usr/src/uts/common/io/yge/yge.h

1066

#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT(8)

usr/src/uts/common/io/yge/yge.h

1067

#define WOL_CTL_ENA_PME_ON_PATTERN BIT(7)

usr/src/uts/common/io/yge/yge.h

1068

#define WOL_CTL_DIS_PME_ON_PATTERN BIT(6)

usr/src/uts/common/io/yge/yge.h

1069

#define WOL_CTL_ENA_LINK_CHG_UNIT BIT(5)

usr/src/uts/common/io/yge/yge.h

1070

#define WOL_CTL_DIS_LINK_CHG_UNIT BIT(4)

usr/src/uts/common/io/yge/yge.h

1071

#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT(3)

usr/src/uts/common/io/yge/yge.h

1072

#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT(2)

usr/src/uts/common/io/yge/yge.h

1073

#define WOL_CTL_ENA_PATTERN_UNIT BIT(1)

usr/src/uts/common/io/yge/yge.h

1074

#define WOL_CTL_DIS_PATTERN_UNIT BIT(0)

usr/src/uts/common/io/yge/yge.h

1085

#define WOL_CTL_PATT_ENA(x) (BIT(0) << (x))

usr/src/uts/common/io/yge/yge.h

1088

#define WOL_PATT_FORCE_PME BIT(7) /* Generates a PME */

usr/src/uts/common/io/yge/yge.h

1133

#define PHY_M_PC_ASS_CRS_TX BIT(11) /* Assert CRS on Transmit */

usr/src/uts/common/io/yge/yge.h

1134

#define PHY_M_PC_FL_GOOD BIT(10) /* Force Link Good */

usr/src/uts/common/io/yge/yge.h

1136

#define PHY_M_PC_ENA_EXT_D BIT(7) /* Enable Ext. Distance (10BT) */

usr/src/uts/common/io/yge/yge.h

1138

#define PHY_M_PC_DIS_125CLK BIT(4) /* Disable 125 CLK */

usr/src/uts/common/io/yge/yge.h

1139

#define PHY_M_PC_MAC_POW_UP BIT(3) /* MAC Power up */

usr/src/uts/common/io/yge/yge.h

1140

#define PHY_M_PC_SQE_T_ENA BIT(2) /* SQE Test Enabled */

usr/src/uts/common/io/yge/yge.h

1141

#define PHY_M_PC_POL_R_DIS BIT(1) /* Polarity Reversal Disabled */

usr/src/uts/common/io/yge/yge.h

1142

#define PHY_M_PC_DIS_JABBER BIT(0) /* Disable Jabber */

usr/src/uts/common/io/yge/yge.h

1154

#define PHY_M_PC_DIS_LINK_P BIT(15) /* Disable Link Pulses */

usr/src/uts/common/io/yge/yge.h

1156

#define PHY_M_PC_DOWN_S_ENA BIT(11) /* Downshift Enable */

usr/src/uts/common/io/yge/yge.h

1158

#define PHY_M_PC_COP_TX_DIS BIT(3)

usr/src/uts/common/io/yge/yge.h

1159

#define PHY_M_PC_POW_D_ENA BIT(2)

usr/src/uts/common/io/yge/yge.h

1166

#define PHY_M_PC_ENA_DTE_DT BIT(15) /* Enable (DTE) Detect */

usr/src/uts/common/io/yge/yge.h

1167

#define PHY_M_PC_ENA_ENE_DT BIT(14) /* Enable Energy Det (sense & pulse) */

usr/src/uts/common/io/yge/yge.h

1168

#define PHY_M_PC_DIS_NLP_CK BIT(13) /* Dis. Normal Link Puls (NLP) Check */

usr/src/uts/common/io/yge/yge.h

1169

#define PHY_M_PC_ENA_LIP_NP BIT(12) /* Enable Link Partner Next Page Reg. */

usr/src/uts/common/io/yge/yge.h

1170

#define PHY_M_PC_DIS_NLP_GN BIT(11) /* Dis. Normal Link Puls Generation */

usr/src/uts/common/io/yge/yge.h

1171

#define PHY_M_PC_DIS_SCRAMB BIT(9) /* Dis. Scrambler */

usr/src/uts/common/io/yge/yge.h

1172

#define PHY_M_PC_DIS_FEFI BIT(8) /* Dis. Far End Fault Indic. (FEFI) */

usr/src/uts/common/io/yge/yge.h

1173

#define PHY_M_PC_SH_TP_SEL BIT(6) /* Shielded Twisted Pair Select */

usr/src/uts/common/io/yge/yge.h

1178

#define PHY_M_PS_SPEED_1000 BIT(15) /* 10 = 1000 Mbps */

usr/src/uts/common/io/yge/yge.h

1179

#define PHY_M_PS_SPEED_100 BIT(14) /* 01 = 100 Mbps */

usr/src/uts/common/io/yge/yge.h

1181

#define PHY_M_PS_FULL_DUP BIT(13) /* Full Duplex */

usr/src/uts/common/io/yge/yge.h

1182

#define PHY_M_PS_PAGE_REC BIT(12) /* Page Received */

usr/src/uts/common/io/yge/yge.h

1183

#define PHY_M_PS_SPDUP_RES BIT(11) /* Speed & Duplex Resolved */

usr/src/uts/common/io/yge/yge.h

1184

#define PHY_M_PS_LINK_UP BIT(10) /* Link Up */

usr/src/uts/common/io/yge/yge.h

1186

#define PHY_M_PS_MDI_X_STAT BIT(6) /* MDI Crossover Stat (1=MDIX) */

usr/src/uts/common/io/yge/yge.h

1187

#define PHY_M_PS_DOWNS_STAT BIT(5) /* Downshift Status (1=downsh.) */

usr/src/uts/common/io/yge/yge.h

1188

#define PHY_M_PS_ENDET_STAT BIT(4) /* Energy Detect Status (1=act) */

usr/src/uts/common/io/yge/yge.h

1189

#define PHY_M_PS_TX_P_EN BIT(3) /* Tx Pause Enabled */

usr/src/uts/common/io/yge/yge.h

1190

#define PHY_M_PS_RX_P_EN BIT(2) /* Rx Pause Enabled */

usr/src/uts/common/io/yge/yge.h

1191

#define PHY_M_PS_POL_REV BIT(1) /* Polarity Reversed */

usr/src/uts/common/io/yge/yge.h

1192

#define PHY_M_PS_JABBER BIT(0) /* Jabber */

usr/src/uts/common/io/yge/yge.h

1197

#define PHY_M_PS_DTE_DETECT BIT(15) /* DTE Detected */

usr/src/uts/common/io/yge/yge.h

1198

#define PHY_M_PS_RES_SPEED BIT(14) /* Resolved Speed (1=100, 0=10) */

usr/src/uts/common/io/yge/yge.h

1202

#define PHY_M_IS_AN_ERROR BIT(15) /* Auto-Negotiation Error */

usr/src/uts/common/io/yge/yge.h

1203

#define PHY_M_IS_LSP_CHANGE BIT(14) /* Link Speed Changed */

usr/src/uts/common/io/yge/yge.h

1204

#define PHY_M_IS_DUP_CHANGE BIT(13) /* Duplex Mode Changed */

usr/src/uts/common/io/yge/yge.h

1205

#define PHY_M_IS_AN_PR BIT(12) /* Page Received */

usr/src/uts/common/io/yge/yge.h

1206

#define PHY_M_IS_AN_COMPL BIT(11) /* Auto-Negotiation Completed */

usr/src/uts/common/io/yge/yge.h

1207

#define PHY_M_IS_LST_CHANGE BIT(10) /* Link Status Changed */

usr/src/uts/common/io/yge/yge.h

1208

#define PHY_M_IS_SYMB_ERROR BIT(9) /* Symbol Error */

usr/src/uts/common/io/yge/yge.h

1209

#define PHY_M_IS_FALSE_CARR BIT(8) /* False Carrier */

usr/src/uts/common/io/yge/yge.h

1210

#define PHY_M_IS_FIFO_ERROR BIT(7) /* FIFO Overflow/Underrun Error */

usr/src/uts/common/io/yge/yge.h

1211

#define PHY_M_IS_MDI_CHANGE BIT(6) /* MDI Crossover Changed */

usr/src/uts/common/io/yge/yge.h

1212

#define PHY_M_IS_DOWNSH_DET BIT(5) /* Downshift Detected */

usr/src/uts/common/io/yge/yge.h

1213

#define PHY_M_IS_END_CHANGE BIT(4) /* Energy Detect Changed */

usr/src/uts/common/io/yge/yge.h

1214

#define PHY_M_IS_DTE_CHANGE BIT(2) /* DTE Power Det. Status Changed */

usr/src/uts/common/io/yge/yge.h

1215

#define PHY_M_IS_POL_CHANGE BIT(1) /* Polarity Changed */

usr/src/uts/common/io/yge/yge.h

1216

#define PHY_M_IS_JABBER BIT(0) /* Jabber */

usr/src/uts/common/io/yge/yge.h

1224

#define PHY_M_EC_ENA_BC_EXT BIT(15) /* Enbl Blck Car. Ext. (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1225

#define PHY_M_EC_ENA_LIN_LB BIT(14) /* Enbl Line Loopback (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1226

#define PHY_M_EC_DIS_LINK_P BIT(12) /* Disable Link Pulses (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1233

#define PHY_M_EC_DOWN_S_ENA BIT(8) /* Downshift Enable (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1235

#define PHY_M_EC_RX_TIM_CT BIT(7) /* RGMII Rx Timing Control */

usr/src/uts/common/io/yge/yge.h

1237

#define PHY_M_EC_FIB_AN_ENA BIT(3) /* Fbr Aut-Neg. Enbl (88E1011S only) */

usr/src/uts/common/io/yge/yge.h

1238

#define PHY_M_EC_DTE_D_ENA BIT(2) /* DTE Detect Enable (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1239

#define PHY_M_EC_TX_TIM_CT BIT(1) /* RGMII Tx Timing Control */

usr/src/uts/common/io/yge/yge.h

1240

#define PHY_M_EC_TRANS_DIS BIT(0) /* Transttr Disable (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1257

#define PHY_M_LEDC_DIS_LED BIT(15) /* Disable LED */

usr/src/uts/common/io/yge/yge.h

1259

#define PHY_M_LEDC_F_INT BIT(11) /* Force Interrupt */

usr/src/uts/common/io/yge/yge.h

1261

#define PHY_M_LEDC_DP_C_LSB BIT(7) /* Duplex Control (LSB, 88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1262

#define PHY_M_LEDC_TX_C_LSB BIT(6) /* Tx Control (LSB, 88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1267

#define PHY_M_LEDC_DP_CTRL BIT(2) /* Duplex Control */

usr/src/uts/common/io/yge/yge.h

1268

#define PHY_M_LEDC_DP_C_MSB BIT(2) /* Duplex Control (MSB, 88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1269

#define PHY_M_LEDC_RX_CTRL BIT(1) /* Rx Activity / Link */

usr/src/uts/common/io/yge/yge.h

1270

#define PHY_M_LEDC_TX_CTRL BIT(0) /* Tx Activity / Link */

usr/src/uts/common/io/yge/yge.h

1271

#define PHY_M_LEDC_TX_C_MSB BIT(0) /* Tx Control (MSB, 88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1307

#define PHY_M_EC2_FI_IMPED BIT(6) /* Fiber Input Impedance */

usr/src/uts/common/io/yge/yge.h

1308

#define PHY_M_EC2_FO_IMPED BIT(5) /* Fiber Output Impedance */

usr/src/uts/common/io/yge/yge.h

1309

#define PHY_M_EC2_FO_M_CLK BIT(4) /* Fiber Mode Clock Enable */

usr/src/uts/common/io/yge/yge.h

1310

#define PHY_M_EC2_FO_BOOST BIT(3) /* Fiber Output Boost */

usr/src/uts/common/io/yge/yge.h

1314

#define PHY_M_FC_AUTO_SEL BIT(15) /* Fiber/Copper Auto Sel. Dis. */

usr/src/uts/common/io/yge/yge.h

1315

#define PHY_M_FC_AN_REG_ACC BIT(14) /* Fiber/Copper AN Reg. Access */

usr/src/uts/common/io/yge/yge.h

1316

#define PHY_M_FC_RESOLUTION BIT(13) /* Fiber/Copper Resolution */

usr/src/uts/common/io/yge/yge.h

1317

#define PHY_M_SER_IF_AN_BP BIT(12) /* Ser. IF AN Bypass Enable */

usr/src/uts/common/io/yge/yge.h

1318

#define PHY_M_SER_IF_BP_ST BIT(11) /* Ser. IF AN Bypass Status */

usr/src/uts/common/io/yge/yge.h

1319

#define PHY_M_IRQ_POLARITY BIT(10) /* IRQ polarity */

usr/src/uts/common/io/yge/yge.h

1320

#define PHY_M_DIS_AUT_MED BIT(9) /* Disable Aut. Medium Reg. Selection */

usr/src/uts/common/io/yge/yge.h

1322

#define PHY_M_UNDOC1 BIT(7) /* undocumented bit !! */

usr/src/uts/common/io/yge/yge.h

1323

#define PHY_M_DTE_POW_STAT BIT(4) /* DTE Power Status (88E1111 only) */

usr/src/uts/common/io/yge/yge.h

1327

#define PHY_M_CABD_ENA_TEST BIT(15) /* Enable Test (Page 0) */

usr/src/uts/common/io/yge/yge.h

1328

#define PHY_M_CABD_DIS_WAIT BIT(15) /* Disable Waiting Period (Page 1) */

usr/src/uts/common/io/yge/yge.h

133

#define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

134

#define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

135

#define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

136

#define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

1369

#define PHY_M_FESC_DIS_WAIT BIT(2) /* Disable TDR Waiting Period */

usr/src/uts/common/io/yge/yge.h

137

#define PCI_Y2_PHY2_POWD BIT(27) /* Set PHY 2 to Power Down (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

1370

#define PHY_M_FESC_ENA_MCLK BIT(1) /* Enable MAC Rx Clock in sleep mode */

usr/src/uts/common/io/yge/yge.h

1371

#define PHY_M_FESC_SEL_CL_A BIT(0) /* Select Class A driver (100B-TX) */

usr/src/uts/common/io/yge/yge.h

1375

#define PHY_M_FIB_FORCE_LNK BIT(10) /* Force Link Good */

usr/src/uts/common/io/yge/yge.h

1376

#define PHY_M_FIB_SIGD_POL BIT(9) /* SIGDET Polarity */

usr/src/uts/common/io/yge/yge.h

1377

#define PHY_M_FIB_TX_DIS BIT(3) /* Transmitter Disable */

usr/src/uts/common/io/yge/yge.h

138

#define PCI_Y2_PHY1_POWD BIT(26) /* Set PHY 1 to Power Down (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

1381

#define PHY_M_MAC_GMIF_PUP BIT(3)

usr/src/uts/common/io/yge/yge.h

139

#define PCI_DIS_BOOT BIT(24) /* Disable BOOT via ROM */

usr/src/uts/common/io/yge/yge.h

140

#define PCI_EN_IO BIT(23) /* Mapping to I/O space */

usr/src/uts/common/io/yge/yge.h

141

#define PCI_EN_FPROM BIT(22) /* Enable FLASH mapping to memory */

usr/src/uts/common/io/yge/yge.h

150

#define PCI_PEX_LEGNAT BIT(15) /* PEX PM legacy/native (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

151

#define PCI_FORCE_BE BIT(14) /* Assert all BEs on MR */

usr/src/uts/common/io/yge/yge.h

152

#define PCI_DIS_MRL BIT(13) /* Disable Mem Read Line */

usr/src/uts/common/io/yge/yge.h

1525

#define GM_GPSR_SPEED BIT(15) /* Port Speed (1 = 100 Mbps) */

usr/src/uts/common/io/yge/yge.h

1526

#define GM_GPSR_DUPLEX BIT(14) /* Duplex Mode (1 = Full) */

usr/src/uts/common/io/yge/yge.h

1527

#define GM_GPSR_FC_TX_DIS BIT(13) /* Tx Flow-Control Mode Disabled */

usr/src/uts/common/io/yge/yge.h

1528

#define GM_GPSR_LINK_UP BIT(12) /* Link Up Status */

usr/src/uts/common/io/yge/yge.h

1529

#define GM_GPSR_PAUSE BIT(11) /* Pause State */

usr/src/uts/common/io/yge/yge.h

153

#define PCI_DIS_MRM BIT(12) /* Disable Mem Read Multiple */

usr/src/uts/common/io/yge/yge.h

1530

#define GM_GPSR_TX_ACTIVE BIT(10) /* Tx in Progress */

usr/src/uts/common/io/yge/yge.h

1531

#define GM_GPSR_EXC_COL BIT(9) /* Excessive Collisions Occured */

usr/src/uts/common/io/yge/yge.h

1532

#define GM_GPSR_LAT_COL BIT(8) /* Late Collisions Occured */

usr/src/uts/common/io/yge/yge.h

1533

#define GM_GPSR_PHY_ST_CH BIT(5) /* PHY Status Change */

usr/src/uts/common/io/yge/yge.h

1534

#define GM_GPSR_GIG_SPEED BIT(4) /* Gigabit Speed (1 = 1000 Mbps) */

usr/src/uts/common/io/yge/yge.h

1535

#define GM_GPSR_PART_MODE BIT(3) /* Partition mode */

usr/src/uts/common/io/yge/yge.h

1536

#define GM_GPSR_FC_RX_DIS BIT(2) /* Rx Flow-Control Mode Disabled */

usr/src/uts/common/io/yge/yge.h

1539

#define GM_GPCR_RMII_PH_ENA BIT(15) /* Enbl RMII for PHY (Yukon-FE only) */

usr/src/uts/common/io/yge/yge.h

154

#define PCI_DIS_MWI BIT(11) /* Disable Mem Write & Invalidate */

usr/src/uts/common/io/yge/yge.h

1540

#define GM_GPCR_RMII_LB_ENA BIT(14) /* Enable RMII Lpbck (Yukon-FE only) */

usr/src/uts/common/io/yge/yge.h

1541

#define GM_GPCR_FC_TX_DIS BIT(13) /* Disable Tx Flow-Control Mode */

usr/src/uts/common/io/yge/yge.h

1542

#define GM_GPCR_TX_ENA BIT(12) /* Enable Transmit */

usr/src/uts/common/io/yge/yge.h

1543

#define GM_GPCR_RX_ENA BIT(11) /* Enable Receive */

usr/src/uts/common/io/yge/yge.h

1544

#define GM_GPCR_LOOP_ENA BIT(9) /* Enable MAC Loopback Mode */

usr/src/uts/common/io/yge/yge.h

1545

#define GM_GPCR_PART_ENA BIT(8) /* Enable Partition Mode */

usr/src/uts/common/io/yge/yge.h

1546

#define GM_GPCR_GIGS_ENA BIT(7) /* Gigabit Speed (1000 Mbps) */

usr/src/uts/common/io/yge/yge.h

1547

#define GM_GPCR_FL_PASS BIT(6) /* Force Link Pass */

usr/src/uts/common/io/yge/yge.h

1548

#define GM_GPCR_DUP_FULL BIT(5) /* Full Duplex Mode */

usr/src/uts/common/io/yge/yge.h

1549

#define GM_GPCR_FC_RX_DIS BIT(4) /* Disable Rx Flow-Control Mode */

usr/src/uts/common/io/yge/yge.h

155

#define PCI_DISC_CLS BIT(10) /* Disc: cacheLsz bound */

usr/src/uts/common/io/yge/yge.h

1550

#define GM_GPCR_SPEED_100 BIT(3) /* Port Speed 100 Mbps */

usr/src/uts/common/io/yge/yge.h

1551

#define GM_GPCR_AU_DUP_DIS BIT(2) /* Disable Auto-Update Duplex */

usr/src/uts/common/io/yge/yge.h

1552

#define GM_GPCR_AU_FCT_DIS BIT(1) /* Disable Auto-Update Flow-C. */

usr/src/uts/common/io/yge/yge.h

1553

#define GM_GPCR_AU_SPD_DIS BIT(0) /* Disable Auto-Update Speed */

usr/src/uts/common/io/yge/yge.h

156

#define PCI_BURST_DIS BIT(9) /* Burst Disable */

usr/src/uts/common/io/yge/yge.h

1560

#define GM_TXCR_FORCE_JAM BIT(15) /* Force Jam / Flow-Control */

usr/src/uts/common/io/yge/yge.h

1561

#define GM_TXCR_CRC_DIS BIT(14) /* Disable insertion of CRC */

usr/src/uts/common/io/yge/yge.h

1562

#define GM_TXCR_PAD_DIS BIT(13) /* Disable padding of packets */

usr/src/uts/common/io/yge/yge.h

157

#define PCI_DIS_PCI_CLK BIT(8) /* Disable PCI clock driving */

usr/src/uts/common/io/yge/yge.h

1571

#define GM_RXCR_UCF_ENA BIT(15) /* Enable Unicast filtering */

usr/src/uts/common/io/yge/yge.h

1572

#define GM_RXCR_MCF_ENA BIT(14) /* Enable Multicast filtering */

usr/src/uts/common/io/yge/yge.h

1573

#define GM_RXCR_CRC_DIS BIT(13) /* Remove 4-byte CRC */

usr/src/uts/common/io/yge/yge.h

1574

#define GM_RXCR_PASS_FC BIT(12) /* Pass FC pckts FIFO (Yukon-1 only) */

usr/src/uts/common/io/yge/yge.h

1596

#define GM_SMOD_LIMIT_4 BIT(10) /* 4 consecutive Tx trials */

usr/src/uts/common/io/yge/yge.h

1597

#define GM_SMOD_VLAN_ENA BIT(9) /* Enable VLAN (Max. Frame Len) */

usr/src/uts/common/io/yge/yge.h

1598

#define GM_SMOD_JUMBO_ENA BIT(8) /* Enable Jumbo (Max. Frame Len) */

usr/src/uts/common/io/yge/yge.h

1599

#define GM_NEW_FLOW_CTRL BIT(6) /* Enable New Flow-Control */

usr/src/uts/common/io/yge/yge.h

160

#define PCI_CLS_OPT BIT(3) /* Cache Line Size PCI-X (YUKON-2) */

usr/src/uts/common/io/yge/yge.h

1611

#define GM_SMI_CT_OP_RD BIT(5) /* OpCode Read (0=Write) */

usr/src/uts/common/io/yge/yge.h

1612

#define GM_SMI_CT_RD_VAL BIT(4) /* Read Valid (Read completed) */

usr/src/uts/common/io/yge/yge.h

1613

#define GM_SMI_CT_BUSY BIT(3) /* Busy (Operation in progress) */

usr/src/uts/common/io/yge/yge.h

1619

#define GM_PAR_MIB_CLR BIT(5) /* Set MIB Clear Counter Mode */

usr/src/uts/common/io/yge/yge.h

1620

#define GM_PAR_MIB_TST BIT(4) /* MIB Load Counter (Test Mode) */

usr/src/uts/common/io/yge/yge.h

1624

#define GMR_FS_VLAN BIT(13) /* VLAN Packet */

usr/src/uts/common/io/yge/yge.h

1625

#define GMR_FS_JABBER BIT(12) /* Jabber Packet */

usr/src/uts/common/io/yge/yge.h

1626

#define GMR_FS_UN_SIZE BIT(11) /* Undersize Packet */

usr/src/uts/common/io/yge/yge.h

1627

#define GMR_FS_MC BIT(10) /* Multicast Packet */

usr/src/uts/common/io/yge/yge.h

1628

#define GMR_FS_BC BIT(9) /* Broadcast Packet */

usr/src/uts/common/io/yge/yge.h

1629

#define GMR_FS_RX_OK BIT(8) /* Receive OK (Good Packet) */

usr/src/uts/common/io/yge/yge.h

1630

#define GMR_FS_GOOD_FC BIT(7) /* Good Flow-Control Packet */

usr/src/uts/common/io/yge/yge.h

1631

#define GMR_FS_BAD_FC BIT(6) /* Bad Flow-Control Packet */

usr/src/uts/common/io/yge/yge.h

1632

#define GMR_FS_MII_ERR BIT(5) /* MII Error */

usr/src/uts/common/io/yge/yge.h

1633

#define GMR_FS_LONG_ERR BIT(4) /* Too Long Packet */

usr/src/uts/common/io/yge/yge.h

1634

#define GMR_FS_FRAGMENT BIT(3) /* Fragment */

usr/src/uts/common/io/yge/yge.h

1635

#define GMR_FS_CRC_ERR BIT(1) /* CRC Error */

usr/src/uts/common/io/yge/yge.h

1636

#define GMR_FS_RX_FF_OV BIT(0) /* Rx FIFO Overflow */

usr/src/uts/common/io/yge/yge.h

1672

#define RX_TRUNC_ON BIT(27) /* enable packet truncation */

usr/src/uts/common/io/yge/yge.h

1673

#define RX_TRUNC_OFF BIT(26) /* disable packet truncation */

usr/src/uts/common/io/yge/yge.h

1674

#define RX_VLAN_STRIP_ON BIT(25) /* enable VLAN stripping */

usr/src/uts/common/io/yge/yge.h

1675

#define RX_VLAN_STRIP_OFF BIT(24) /* disable VLAN stripping */

usr/src/uts/common/io/yge/yge.h

1676

#define GMF_RX_OVER_ON BIT(19) /* flushing on receive overrun */

usr/src/uts/common/io/yge/yge.h

1677

#define GMF_RX_OVER_OFF BIT(18) /* flushing on receive overrun */

usr/src/uts/common/io/yge/yge.h

1678

#define GMF_WP_TST_ON BIT(14) /* Write Pointer Test On */

usr/src/uts/common/io/yge/yge.h

1679

#define GMF_WP_TST_OFF BIT(13) /* Write Pointer Test Off */

usr/src/uts/common/io/yge/yge.h

168

#define PCI_PATCH_DIR_3 BIT(11)

usr/src/uts/common/io/yge/yge.h

1680

#define GMF_WP_STEP BIT(12) /* Write Pointer Step/Increment */

usr/src/uts/common/io/yge/yge.h

1681

#define GMF_RP_TST_ON BIT(10) /* Read Pointer Test On */

usr/src/uts/common/io/yge/yge.h

1682

#define GMF_RP_TST_OFF BIT(9) /* Read Pointer Test Off */

usr/src/uts/common/io/yge/yge.h

1683

#define GMF_RP_STEP BIT(8) /* Read Pointer Step/Increment */

usr/src/uts/common/io/yge/yge.h

1684

#define GMF_RX_F_FL_ON BIT(7) /* Rx FIFO Flush Mode On */

usr/src/uts/common/io/yge/yge.h

1685

#define GMF_RX_F_FL_OFF BIT(6) /* Rx FIFO Flush Mode Off */

usr/src/uts/common/io/yge/yge.h

1686

#define GMF_CLI_RX_FO BIT(5) /* Clear IRQ Rx FIFO Overrun */

usr/src/uts/common/io/yge/yge.h

1687

#define GMF_CLI_RX_FC BIT(4) /* Clear IRQ Rx Frame Complete */

usr/src/uts/common/io/yge/yge.h

1688

#define GMF_OPER_ON BIT(3) /* Operational Mode On */

usr/src/uts/common/io/yge/yge.h

1689

#define GMF_OPER_OFF BIT(2) /* Operational Mode Off */

usr/src/uts/common/io/yge/yge.h

169

#define PCI_PATCH_DIR_2 BIT(10)

usr/src/uts/common/io/yge/yge.h

1690

#define GMF_RST_CLR BIT(1) /* Clear GMAC FIFO Reset */

usr/src/uts/common/io/yge/yge.h

1691

#define GMF_RST_SET BIT(0) /* Set GMAC FIFO Reset */

usr/src/uts/common/io/yge/yge.h

1694

#define TX_STFW_DIS BIT(31) /* Disable Store & Forward (Yukon-EC Ultra) */

usr/src/uts/common/io/yge/yge.h

1695

#define TX_STFW_ENA BIT(30) /* Enable Store & Forward (Yukon-EC Ultra) */

usr/src/uts/common/io/yge/yge.h

1696

#define TX_VLAN_TAG_ON BIT(25) /* enable VLAN tagging */

usr/src/uts/common/io/yge/yge.h

1697

#define TX_VLAN_TAG_OFF BIT(24) /* disable VLAN tagging */

usr/src/uts/common/io/yge/yge.h

1698

#define TX_JUMBO_ENA BIT(23) /* Enable Jumbo Mode (Yukon-EC Ultra) */

usr/src/uts/common/io/yge/yge.h

1699

#define TX_JUMBO_DIS BIT(22) /* Disable Jumbo Mode (Yukon-EC Ultra) */

usr/src/uts/common/io/yge/yge.h

170

#define PCI_PATCH_DIR_1 BIT(9)

usr/src/uts/common/io/yge/yge.h

1700

#define GMF_WSP_TST_ON BIT(18) /* Write Shadow Pointer Test On */

usr/src/uts/common/io/yge/yge.h

1701

#define GMF_WSP_TST_OFF BIT(17) /* Write Shadow Pointer Test Off */

usr/src/uts/common/io/yge/yge.h

1702

#define GMF_WSP_STEP BIT(16) /* Write Shadow Pointer Step/Increment */

usr/src/uts/common/io/yge/yge.h

1704

#define GMF_CLI_TX_FU BIT(6) /* Clear IRQ Tx FIFO Underrun */

usr/src/uts/common/io/yge/yge.h

1705

#define GMF_CLI_TX_FC BIT(5) /* Clear IRQ Tx Frame Complete */

usr/src/uts/common/io/yge/yge.h

1706

#define GMF_CLI_TX_PE BIT(4) /* Clear IRQ Tx Parity Error */

usr/src/uts/common/io/yge/yge.h

171

#define PCI_PATCH_DIR_0 BIT(8)

usr/src/uts/common/io/yge/yge.h

1716

#define GMT_ST_START BIT(2) /* Start Time Stamp Timer */

usr/src/uts/common/io/yge/yge.h

1717

#define GMT_ST_STOP BIT(1) /* Stop Time Stamp Timer */

usr/src/uts/common/io/yge/yge.h

1718

#define GMT_ST_CLR_IRQ BIT(0) /* Clear Time Stamp Timer IRQ */

usr/src/uts/common/io/yge/yge.h

1721

#define PC_CLR_IRQ_CHK BIT(5) /* Clear IRQ Check */

usr/src/uts/common/io/yge/yge.h

1722

#define PC_POLL_RQ BIT(4) /* Poll Request Start */

usr/src/uts/common/io/yge/yge.h

1723

#define PC_POLL_OP_ON BIT(3) /* Operational Mode On */

usr/src/uts/common/io/yge/yge.h

1724

#define PC_POLL_OP_OFF BIT(2) /* Operational Mode Off */

usr/src/uts/common/io/yge/yge.h

1725

#define PC_POLL_RST_CLR BIT(1) /* Clear Polling Unit Reset (Enable) */

usr/src/uts/common/io/yge/yge.h

1726

#define PC_POLL_RST_SET BIT(0) /* Set Polling Unit Reset */

usr/src/uts/common/io/yge/yge.h

173

#define PCI_EXT_PATCH_3 BIT(7)

usr/src/uts/common/io/yge/yge.h

1730

#define Y2_ASF_AHB_RST BIT(9) /* AHB bridge reset */

usr/src/uts/common/io/yge/yge.h

1731

#define Y2_ASF_CPU_MODE BIT(8) /* ASF CPU reset mode */

usr/src/uts/common/io/yge/yge.h

1732

#define Y2_ASF_OS_PRES BIT(4) /* ASF operation system present */

usr/src/uts/common/io/yge/yge.h

1733

#define Y2_ASF_RESET BIT(3) /* ASF system in reset state */

usr/src/uts/common/io/yge/yge.h

1734

#define Y2_ASF_RUNNING BIT(2) /* ASF system operational */

usr/src/uts/common/io/yge/yge.h

1735

#define Y2_ASF_CLR_HSTI BIT(1) /* Clear ASF IRQ */

usr/src/uts/common/io/yge/yge.h

1736

#define Y2_ASF_IRQ BIT(0) /* Issue an IRQ to ASF system */

usr/src/uts/common/io/yge/yge.h

174

#define PCI_EXT_PATCH_2 BIT(6)

usr/src/uts/common/io/yge/yge.h

1744

#define Y2_ASF_CLR_ASFI BIT(1) /* Clear host IRQ */

usr/src/uts/common/io/yge/yge.h

1745

#define Y2_ASF_HOST_IRQ BIT(0) /* Issue an IRQ to HOST system */

usr/src/uts/common/io/yge/yge.h

1748

#define SC_STAT_CLR_IRQ BIT(4) /* Status Burst IRQ clear */

usr/src/uts/common/io/yge/yge.h

1749

#define SC_STAT_OP_ON BIT(3) /* Operational Mode On */

usr/src/uts/common/io/yge/yge.h

175

#define PCI_EXT_PATCH_1 BIT(5)

usr/src/uts/common/io/yge/yge.h

1750

#define SC_STAT_OP_OFF BIT(2) /* Operational Mode Off */

usr/src/uts/common/io/yge/yge.h

1751

#define SC_STAT_RST_CLR BIT(1) /* Clear Status Unit Reset (Enable) */

usr/src/uts/common/io/yge/yge.h

1752

#define SC_STAT_RST_SET BIT(0) /* Set Status Unit Reset */

usr/src/uts/common/io/yge/yge.h

1755

#define GMC_SET_RST BIT(15) /* MAC SEC RST */

usr/src/uts/common/io/yge/yge.h

1756

#define GMC_SEC_RST_OFF BIT(14) /* MAC SEC RST OFF */

usr/src/uts/common/io/yge/yge.h

1757

#define GMC_BYP_MACSECRX_ON BIT(13) /* Bypass macsec RX */

usr/src/uts/common/io/yge/yge.h

1758

#define GMC_BYP_MACSECRX_OFF BIT(12) /* Bypass macsec RX off */

usr/src/uts/common/io/yge/yge.h

1759

#define GMC_BYP_MACSECTX_ON BIT(11) /* Bypass macsec TX */

usr/src/uts/common/io/yge/yge.h

176

#define PCI_EXT_PATCH_0 BIT(4)

usr/src/uts/common/io/yge/yge.h

1760

#define GMC_BYP_MACSECTX_OFF BIT(10) /* Bypass macsec TX off */

usr/src/uts/common/io/yge/yge.h

1761

#define GMC_BYP_RETR_ON BIT(9) /* Bypass retransmit FIFO On */

usr/src/uts/common/io/yge/yge.h

1762

#define GMC_BYP_RETR_OFF BIT(8) /* Bypass retransmit FIFO Off */

usr/src/uts/common/io/yge/yge.h

1763

#define GMC_H_BURST_ON BIT(7) /* Half Duplex Burst Mode On */

usr/src/uts/common/io/yge/yge.h

1764

#define GMC_H_BURST_OFF BIT(6) /* Half Duplex Burst Mode Off */

usr/src/uts/common/io/yge/yge.h

1765

#define GMC_F_LOOPB_ON BIT(5) /* FIFO Loopback On */

usr/src/uts/common/io/yge/yge.h

1766

#define GMC_F_LOOPB_OFF BIT(4) /* FIFO Loopback Off */

usr/src/uts/common/io/yge/yge.h

1767

#define GMC_PAUSE_ON BIT(3) /* Pause On */

usr/src/uts/common/io/yge/yge.h

1768

#define GMC_PAUSE_OFF BIT(2) /* Pause Off */

usr/src/uts/common/io/yge/yge.h

1769

#define GMC_RST_CLR BIT(1) /* Clear GMAC Reset */

usr/src/uts/common/io/yge/yge.h

177

#define PCI_EN_DUMMY_RD BIT(3) /* Enable Dummy Read */

usr/src/uts/common/io/yge/yge.h

1770

#define GMC_RST_SET BIT(0) /* Set GMAC Reset */

usr/src/uts/common/io/yge/yge.h

1773

#define GPC_SEL_BDT BIT(28) /* Select Bi-Dir. Transfer for MDC/MDIO */

usr/src/uts/common/io/yge/yge.h

1774

#define GPC_INT_POL BIT(27) /* IRQ Polarity is Active Low */

usr/src/uts/common/io/yge/yge.h

1775

#define GPC_75_OHM BIT(26) /* Use 75 Ohm Termination instead of 50 */

usr/src/uts/common/io/yge/yge.h

1776

#define GPC_DIS_FC BIT(25) /* Disable Automatic Fiber/Copper Detection */

usr/src/uts/common/io/yge/yge.h

1777

#define GPC_DIS_SLEEP BIT(24) /* Disable Energy Detect */

usr/src/uts/common/io/yge/yge.h

1778

#define GPC_HWCFG_M_3 BIT(23) /* HWCFG_MODE[3] */

usr/src/uts/common/io/yge/yge.h

1779

#define GPC_HWCFG_M_2 BIT(22) /* HWCFG_MODE[2] */

usr/src/uts/common/io/yge/yge.h

178

#define PCI_REV_DESC BIT(2) /* Reverse Desc. Bytes */

usr/src/uts/common/io/yge/yge.h

1780

#define GPC_HWCFG_M_1 BIT(21) /* HWCFG_MODE[1] */

usr/src/uts/common/io/yge/yge.h

1781

#define GPC_HWCFG_M_0 BIT(20) /* HWCFG_MODE[0] */

usr/src/uts/common/io/yge/yge.h

1782

#define GPC_ANEG_0 BIT(19) /* ANEG[0] */

usr/src/uts/common/io/yge/yge.h

1783

#define GPC_ENA_XC BIT(18) /* Enable MDI crossover */

usr/src/uts/common/io/yge/yge.h

1784

#define GPC_DIS_125 BIT(17) /* Disable 125 MHz clock */

usr/src/uts/common/io/yge/yge.h

1785

#define GPC_ANEG_3 BIT(16) /* ANEG[3] */

usr/src/uts/common/io/yge/yge.h

1786

#define GPC_ANEG_2 BIT(15) /* ANEG[2] */

usr/src/uts/common/io/yge/yge.h

1787

#define GPC_ANEG_1 BIT(14) /* ANEG[1] */

usr/src/uts/common/io/yge/yge.h

1788

#define GPC_ENA_PAUSE BIT(13) /* Enable Pause (SYM_OR_REM) */

usr/src/uts/common/io/yge/yge.h

1789

#define GPC_PHYADDR_4 BIT(12) /* Bit 4 of Phy Addr */

usr/src/uts/common/io/yge/yge.h

179

#define PCI_USEDATA64 BIT(0) /* Use 64Bit Data bus ext */

usr/src/uts/common/io/yge/yge.h

1790

#define GPC_PHYADDR_3 BIT(11) /* Bit 3 of Phy Addr */

usr/src/uts/common/io/yge/yge.h

1791

#define GPC_PHYADDR_2 BIT(10) /* Bit 2 of Phy Addr */

usr/src/uts/common/io/yge/yge.h

1792

#define GPC_PHYADDR_1 BIT(9) /* Bit 1 of Phy Addr */

usr/src/uts/common/io/yge/yge.h

1793

#define GPC_PHYADDR_0 BIT(8) /* Bit 0 of Phy Addr */

usr/src/uts/common/io/yge/yge.h

1794

#define GPC_RST_CLR BIT(1) /* Clear GPHY Reset */

usr/src/uts/common/io/yge/yge.h

1795

#define GPC_RST_SET BIT(0) /* Set GPHY Reset */

usr/src/uts/common/io/yge/yge.h

1799

#define GM_IS_RX_CO_OV BIT(5) /* Receive Counter Overflow IRQ */

usr/src/uts/common/io/yge/yge.h

1800

#define GM_IS_TX_CO_OV BIT(4) /* Transmit Counter Overflow IRQ */

usr/src/uts/common/io/yge/yge.h

1801

#define GM_IS_TX_FF_UR BIT(3) /* Transmit FIFO Underrun */

usr/src/uts/common/io/yge/yge.h

1802

#define GM_IS_TX_COMPL BIT(2) /* Frame Transmission Complete */

usr/src/uts/common/io/yge/yge.h

1803

#define GM_IS_RX_FF_OR BIT(1) /* Receive FIFO Overrun */

usr/src/uts/common/io/yge/yge.h

1804

#define GM_IS_RX_COMPL BIT(0) /* Frame Reception Complete */

usr/src/uts/common/io/yge/yge.h

1809

#define GMLC_RST_CLR BIT(1) /* Clear GMAC Link Reset */

usr/src/uts/common/io/yge/yge.h

1810

#define GMLC_RST_SET BIT(0) /* Set GMAC Link Reset */

usr/src/uts/common/io/yge/yge.h

182

#define PCI_OS_PCI64B BIT(31) /* Conventional PCI 64 bits Bus */

usr/src/uts/common/io/yge/yge.h

183

#define PCI_OS_PCIX BIT(30) /* PCI-X Bus */

usr/src/uts/common/io/yge/yge.h

185

#define PCI_OS_PCI66M BIT(27) /* PCI 66 MHz Bus */

usr/src/uts/common/io/yge/yge.h

186

#define PCI_OS_PCI_X BIT(26) /* PCI/PCI-X Bus (0 = PEX) */

usr/src/uts/common/io/yge/yge.h

200

#define PCI_FORCE_ASPM_REQUEST BIT(15) /* Force ASPM Request (A1 only) */

usr/src/uts/common/io/yge/yge.h

2003

#define BMU_OWN BIT(31) /* OWN bit: 0=host/1=BMU */

usr/src/uts/common/io/yge/yge.h

2004

#define BMU_STF BIT(30) /* Start of Frame */

usr/src/uts/common/io/yge/yge.h

2005

#define BMU_EOF BIT(29) /* End of Frame */

usr/src/uts/common/io/yge/yge.h

2006

#define BMU_IRQ_EOB BIT(28) /* Req "End of Buffer" IRQ */

usr/src/uts/common/io/yge/yge.h

2007

#define BMU_IRQ_EOF BIT(27) /* Req "End of Frame" IRQ */

usr/src/uts/common/io/yge/yge.h

2009

#define BMU_STFWD BIT(26) /* (Tx) Store & Forward Frame */

usr/src/uts/common/io/yge/yge.h

201

#define PCI_ASPM_GPHY_LINK_DOWN BIT(14) /* GPHY Link Down (A1 only) */

usr/src/uts/common/io/yge/yge.h

2010

#define BMU_NO_FCS BIT(25) /* (Tx) Disable MAC FCS (CRC) generation */

usr/src/uts/common/io/yge/yge.h

2011

#define BMU_SW BIT(24) /* (Tx) 1 bit res. for SW use */

usr/src/uts/common/io/yge/yge.h

2013

#define BMU_DEV_0 BIT(26) /* (Rx) Transfer data to Dev0 */

usr/src/uts/common/io/yge/yge.h

2014

#define BMU_STAT_VAL BIT(25) /* (Rx) Rx Status Valid */

usr/src/uts/common/io/yge/yge.h

2015

#define BMU_TIST_VAL BIT(24) /* (Rx) Rx TimeStamp Valid */

usr/src/uts/common/io/yge/yge.h

202

#define PCI_ASPM_INT_FIFO_EMPTY BIT(13) /* Internal FIFO Empty (A1 only) */

usr/src/uts/common/io/yge/yge.h

203

#define PCI_ASPM_CLKRUN_REQUEST BIT(12) /* CLKRUN Request (A1 only) */

usr/src/uts/common/io/yge/yge.h

204

#define PCI_ASPM_FORCE_CLKREQ_ENA BIT(4) /* Frc CLKRQ Enbl (A1b only) */

usr/src/uts/common/io/yge/yge.h

205

#define PCI_ASPM_CLKREQ_PAD_CTL BIT(3) /* CLKREQ PAD Control (A1 only) */

usr/src/uts/common/io/yge/yge.h

206

#define PCI_ASPM_A1_MODE_SELECT BIT(2) /* A1 Mode Select (A1 only) */

usr/src/uts/common/io/yge/yge.h

207

#define PCI_CLK_GATE_PEX_UNIT_ENA BIT(1) /* Enable Gate PEX Unit Clock */

usr/src/uts/common/io/yge/yge.h

208

#define PCI_CLK_GATE_ROOT_COR_ENA BIT(0) /* Enbl Gate Root Core Clock */

usr/src/uts/common/io/yge/yge.h

217

#define PEX_DC_EN_NO_SNOOP BIT(11) /* Enable No Snoop */

usr/src/uts/common/io/yge/yge.h

218

#define PEX_DC_EN_AUX_POW BIT(10) /* Enable AUX Power */

usr/src/uts/common/io/yge/yge.h

219

#define PEX_DC_EN_PHANTOM BIT(9) /* Enable Phantom Functions */

usr/src/uts/common/io/yge/yge.h

220

#define PEX_DC_EN_EXT_TAG BIT(8) /* Enable Extended Tag Field */

usr/src/uts/common/io/yge/yge.h

222

#define PEX_DC_EN_REL_ORD BIT(4) /* Enable Relaxed Ordering */

usr/src/uts/common/io/yge/yge.h

223

#define PEX_DC_EN_UNS_RQ_RP BIT(3) /* Enable Unsupported Request Report */

usr/src/uts/common/io/yge/yge.h

224

#define PEX_DC_EN_FAT_ER_RP BIT(2) /* Enable Fatal Error Report */

usr/src/uts/common/io/yge/yge.h

225

#define PEX_DC_EN_NFA_ER_RP BIT(1) /* Enable Non-Fatal Error Report */

usr/src/uts/common/io/yge/yge.h

226

#define PEX_DC_EN_COR_ER_RP BIT(0) /* Enable Correctable Error Report */

usr/src/uts/common/io/yge/yge.h

231

#define PEX_LS_SLOT_CLK_CFG BIT(12) /* Slot Clock Config */

usr/src/uts/common/io/yge/yge.h

232

#define PEX_LS_LINK_TRAIN BIT(11) /* Link Training */

usr/src/uts/common/io/yge/yge.h

233

#define PEX_LS_TRAIN_ERROR BIT(10) /* Training Error */

usr/src/uts/common/io/yge/yge.h

238

#define PEX_UNSUP_REQ BIT(20) /* Unsupported Request Error */

usr/src/uts/common/io/yge/yge.h

239

#define PEX_MALFOR_TLP BIT(18) /* Malformed TLP */

usr/src/uts/common/io/yge/yge.h

240

#define PEX_RX_OV BIT(17) /* Receiver Overflow (not supported) */

usr/src/uts/common/io/yge/yge.h

241

#define PEX_UNEXP_COMP BIT(16) /* Unexpected Completion */

usr/src/uts/common/io/yge/yge.h

242

#define PEX_COMP_TO BIT(14) /* Completion Timeout */

usr/src/uts/common/io/yge/yge.h

243

#define PEX_FLOW_CTRL_P BIT(13) /* Flow Control Protocol Error */

usr/src/uts/common/io/yge/yge.h

244

#define PEX_POIS_TLP BIT(12) /* Poisoned TLP */

usr/src/uts/common/io/yge/yge.h

245

#define PEX_DATA_LINK_P BIT(4) /* Data Link Protocol Error */

usr/src/uts/common/io/yge/yge.h

611

#define Y2_VMAIN_AVAIL BIT(17) /* VMAIN available (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

612

#define Y2_VAUX_AVAIL BIT(16) /* VAUX available (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

613

#define Y2_HW_WOL_ON BIT(15) /* HW WOL On (Yukon-EC Ultra A1 only) */

usr/src/uts/common/io/yge/yge.h

614

#define Y2_HW_WOL_OFF BIT(14) /* HW WOL Off (Yukon-EC Ultra A1 only) */

usr/src/uts/common/io/yge/yge.h

615

#define Y2_ASF_ENABLE BIT(13) /* ASF Unit Enable (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

616

#define Y2_ASF_DISABLE BIT(12) /* ASF Unit Disable (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

617

#define Y2_CLK_RUN_ENA BIT(11) /* CLK_RUN Enable (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

618

#define Y2_CLK_RUN_DIS BIT(10) /* CLK_RUN Disable (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

619

#define Y2_LED_STAT_ON BIT(9) /* Status LED On (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

620

#define Y2_LED_STAT_OFF BIT(8) /* Status LED Off (YUKON-2 only) */

usr/src/uts/common/io/yge/yge.h

621

#define CS_ST_SW_IRQ BIT(7) /* Set IRQ SW Request */

usr/src/uts/common/io/yge/yge.h

622

#define CS_CL_SW_IRQ BIT(6) /* Clear IRQ SW Request */

usr/src/uts/common/io/yge/yge.h

623

#define CS_STOP_DONE BIT(5) /* Stop Master is finished */

usr/src/uts/common/io/yge/yge.h

624

#define CS_STOP_MAST BIT(4) /* Command Bit to stop the master */

usr/src/uts/common/io/yge/yge.h

625

#define CS_MRST_CLR BIT(3) /* Clear Master Reset */

usr/src/uts/common/io/yge/yge.h

626

#define CS_MRST_SET BIT(2) /* Set Master Reset */

usr/src/uts/common/io/yge/yge.h

627

#define CS_RST_CLR BIT(1) /* Clear Software Reset */

usr/src/uts/common/io/yge/yge.h

628

#define CS_RST_SET BIT(0) /* Set Software Reset */

usr/src/uts/common/io/yge/yge.h

630

#define LED_STAT_ON BIT(1) /* Status LED On */

usr/src/uts/common/io/yge/yge.h

631

#define LED_STAT_OFF BIT(0) /* Status LED Off */

usr/src/uts/common/io/yge/yge.h

634

#define PC_VAUX_ENA BIT(7) /* Switch VAUX Enable */

usr/src/uts/common/io/yge/yge.h

635

#define PC_VAUX_DIS BIT(6) /* Switch VAUX Disable */

usr/src/uts/common/io/yge/yge.h

636

#define PC_VCC_ENA BIT(5) /* Switch VCC Enable */

usr/src/uts/common/io/yge/yge.h

637

#define PC_VCC_DIS BIT(4) /* Switch VCC Disable */

usr/src/uts/common/io/yge/yge.h

638

#define PC_VAUX_ON BIT(3) /* Switch VAUX On */

usr/src/uts/common/io/yge/yge.h

639

#define PC_VAUX_OFF BIT(2) /* Switch VAUX Off */

usr/src/uts/common/io/yge/yge.h

640

#define PC_VCC_ON BIT(1) /* Switch VCC On */

usr/src/uts/common/io/yge/yge.h

641

#define PC_VCC_OFF BIT(0) /* Switch VCC Off */

usr/src/uts/common/io/yge/yge.h

652

#define Y2_IS_HW_ERR BIT(31) /* Interrupt HW Error */

usr/src/uts/common/io/yge/yge.h

653

#define Y2_IS_STAT_BMU BIT(30) /* Status BMU Interrupt */

usr/src/uts/common/io/yge/yge.h

654

#define Y2_IS_ASF BIT(29) /* ASF subsystem Interrupt */

usr/src/uts/common/io/yge/yge.h

655

#define Y2_IS_POLL_CHK BIT(27) /* Check IRQ from polling unit */

usr/src/uts/common/io/yge/yge.h

656

#define Y2_IS_TWSI_RDY BIT(26) /* IRQ on end of TWSI Tx */

usr/src/uts/common/io/yge/yge.h

657

#define Y2_IS_IRQ_SW BIT(25) /* SW forced IRQ */

usr/src/uts/common/io/yge/yge.h

658

#define Y2_IS_TIMINT BIT(24) /* IRQ from Timer */

usr/src/uts/common/io/yge/yge.h

659

#define Y2_IS_IRQ_PHY2 BIT(12) /* Interrupt from PHY 2 */

usr/src/uts/common/io/yge/yge.h

660

#define Y2_IS_IRQ_MAC2 BIT(11) /* Interrupt from MAC 2 */

usr/src/uts/common/io/yge/yge.h

661

#define Y2_IS_CHK_RX2 BIT(10) /* Descriptor error Rx 2 */

usr/src/uts/common/io/yge/yge.h

662

#define Y2_IS_CHK_TXS2 BIT(9) /* Descriptor error TXS 2 */

usr/src/uts/common/io/yge/yge.h

663

#define Y2_IS_CHK_TXA2 BIT(8) /* Descriptor error TXA 2 */

usr/src/uts/common/io/yge/yge.h

664

#define Y2_IS_IRQ_PHY1 BIT(4) /* Interrupt from PHY 1 */

usr/src/uts/common/io/yge/yge.h

665

#define Y2_IS_IRQ_MAC1 BIT(3) /* Interrupt from MAC 1 */

usr/src/uts/common/io/yge/yge.h

666

#define Y2_IS_CHK_RX1 BIT(2) /* Descriptor error Rx 1 */

usr/src/uts/common/io/yge/yge.h

667

#define Y2_IS_CHK_TXS1 BIT(1) /* Descriptor error TXS 1 */

usr/src/uts/common/io/yge/yge.h

668

#define Y2_IS_CHK_TXA1 BIT(0) /* Descriptor error TXA 1 */

usr/src/uts/common/io/yge/yge.h

682

#define Y2_IS_TIST_OV BIT(29) /* Time Stamp Timer overflow interrupt */

usr/src/uts/common/io/yge/yge.h

683

#define Y2_IS_SENSOR BIT(28) /* Sensor interrupt */

usr/src/uts/common/io/yge/yge.h

684

#define Y2_IS_MST_ERR BIT(27) /* Master error interrupt */

usr/src/uts/common/io/yge/yge.h

685

#define Y2_IS_IRQ_STAT BIT(26) /* Status exception interrupt */

usr/src/uts/common/io/yge/yge.h

686

#define Y2_IS_PCI_EXP BIT(25) /* PCI-Express interrupt */

usr/src/uts/common/io/yge/yge.h

687

#define Y2_IS_PCI_NEXP BIT(24) /* PCI-Express error similar to PCI error */

usr/src/uts/common/io/yge/yge.h

688

#define Y2_IS_PAR_RD2 BIT(13) /* Read RAM parity error interrupt */

usr/src/uts/common/io/yge/yge.h

689

#define Y2_IS_PAR_WR2 BIT(12) /* Write RAM parity error interrupt */

usr/src/uts/common/io/yge/yge.h

690

#define Y2_IS_PAR_MAC2 BIT(11) /* MAC hardware fault interrupt */

usr/src/uts/common/io/yge/yge.h

691

#define Y2_IS_PAR_RX2 BIT(10) /* Parity Error Rx Queue 2 */

usr/src/uts/common/io/yge/yge.h

692

#define Y2_IS_TCP_TXS2 BIT(9) /* TCP length mismatch sync Tx queue IRQ */

usr/src/uts/common/io/yge/yge.h

693

#define Y2_IS_TCP_TXA2 BIT(8) /* TCP length mismatch async Tx queue IRQ */

usr/src/uts/common/io/yge/yge.h

694

#define Y2_IS_PAR_RD1 BIT(5) /* Read RAM parity error interrupt */

usr/src/uts/common/io/yge/yge.h

695

#define Y2_IS_PAR_WR1 BIT(4) /* Write RAM parity error interrupt */

usr/src/uts/common/io/yge/yge.h

696

#define Y2_IS_PAR_MAC1 BIT(3) /* MAC hardware fault interrupt */

usr/src/uts/common/io/yge/yge.h

697

#define Y2_IS_PAR_RX1 BIT(2) /* Parity Error Rx Queue 1 */

usr/src/uts/common/io/yge/yge.h

698

#define Y2_IS_TCP_TXS1 BIT(1) /* TCP length mismatch sync Tx queue IRQ */

usr/src/uts/common/io/yge/yge.h

699

#define Y2_IS_TCP_TXA1 BIT(0) /* TCP length mismatch async Tx queue IRQ */

usr/src/uts/common/io/yge/yge.h

712

#define CFG_DIS_M2_CLK BIT(1) /* Disable Clock for 2nd MAC */

usr/src/uts/common/io/yge/yge.h

713

#define CFG_SNG_MAC BIT(0) /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */

usr/src/uts/common/io/yge/yge.h

763

#define Y2_STATUS_LNK2_INAC BIT(7) /* Status Link 2 inactiv (0 = activ) */

usr/src/uts/common/io/yge/yge.h

764

#define Y2_CLK_GAT_LNK2_DIS BIT(6) /* Disable clock gating Link 2 */

usr/src/uts/common/io/yge/yge.h

765

#define Y2_COR_CLK_LNK2_DIS BIT(5) /* Disable Core clock Link 2 */

usr/src/uts/common/io/yge/yge.h

766

#define Y2_PCI_CLK_LNK2_DIS BIT(4) /* Disable PCI clock Link 2 */

usr/src/uts/common/io/yge/yge.h

767

#define Y2_STATUS_LNK1_INAC BIT(3) /* Status Link 1 inactiv (0 = activ) */

usr/src/uts/common/io/yge/yge.h

768

#define Y2_CLK_GAT_LNK1_DIS BIT(2) /* Disable clock gating Link 1 */

usr/src/uts/common/io/yge/yge.h

769

#define Y2_COR_CLK_LNK1_DIS BIT(1) /* Disable Core clock Link 1 */

usr/src/uts/common/io/yge/yge.h

770

#define Y2_PCI_CLK_LNK1_DIS BIT(0) /* Disable PCI clock Link 1 */

usr/src/uts/common/io/yge/yge.h

774

#define CFG_LINK_2_AVAIL BIT(1) /* Link 2 available */

usr/src/uts/common/io/yge/yge.h

775

#define CFG_LINK_1_AVAIL BIT(0) /* Link 1 available */

usr/src/uts/common/io/yge/yge.h

792

#define Y2_CLK_DIV_ENA BIT(1) /* Enable Core Clock Division */

usr/src/uts/common/io/yge/yge.h

793

#define Y2_CLK_DIV_DIS BIT(0) /* Disable Core Clock Division */

usr/src/uts/common/io/yge/yge.h

797

#define TIM_START BIT(2) /* Start Timer */

usr/src/uts/common/io/yge/yge.h

798

#define TIM_STOP BIT(1) /* Stop Timer */

usr/src/uts/common/io/yge/yge.h

799

#define TIM_CLR_IRQ BIT(0) /* Clear Timer IRQ (!IRQM) */

usr/src/uts/common/io/yge/yge.h

804

#define TIM_T_ON BIT(2) /* Test mode on */

usr/src/uts/common/io/yge/yge.h

805

#define TIM_T_OFF BIT(1) /* Test mode off */

usr/src/uts/common/io/yge/yge.h

806

#define TIM_T_STEP BIT(0) /* Test step */

usr/src/uts/common/io/yge/yge.h

813

#define DPT_START BIT(1) /* Start Descriptor Poll Timer */

usr/src/uts/common/io/yge/yge.h

814

#define DPT_STOP BIT(0) /* Stop Descriptor Poll Timer */

usr/src/uts/common/io/yge/yge.h

817

#define TST_FRC_DPERR_MR BIT(7) /* force DATAPERR on MST RD */

usr/src/uts/common/io/yge/yge.h

818

#define TST_FRC_DPERR_MW BIT(6) /* force DATAPERR on MST WR */

usr/src/uts/common/io/yge/yge.h

819

#define TST_FRC_DPERR_TR BIT(5) /* force DATAPERR on TRG RD */

usr/src/uts/common/io/yge/yge.h

820

#define TST_FRC_DPERR_TW BIT(4) /* force DATAPERR on TRG WR */

usr/src/uts/common/io/yge/yge.h

821

#define TST_FRC_APERR_M BIT(3) /* force ADDRPERR on MST */

usr/src/uts/common/io/yge/yge.h

822

#define TST_FRC_APERR_T BIT(2) /* force ADDRPERR on TRG */

usr/src/uts/common/io/yge/yge.h

823

#define TST_CFG_WRITE_ON BIT(1) /* Enable Config Reg WR */

usr/src/uts/common/io/yge/yge.h

824

#define TST_CFG_WRITE_OFF BIT(0) /* Disable Config Reg WR */

usr/src/uts/common/io/yge/yge.h

827

#define I2C_FLAG BIT(31) /* Start read/write if WR */

usr/src/uts/common/io/yge/yge.h

830

#define I2C_BURST_LEN BIT(4) /* Burst Len, 1/4 bytes */

usr/src/uts/common/io/yge/yge.h

840

#define I2C_STOP BIT(0) /* Interrupt I2C transfer */

usr/src/uts/common/io/yge/yge.h

843

#define I2C_CLR_IRQ BIT(0) /* Clear I2C IRQ */

usr/src/uts/common/io/yge/yge.h

846

#define I2C_DATA_DIR BIT(2) /* direction of I2C_DATA */

usr/src/uts/common/io/yge/yge.h

847

#define I2C_DATA BIT(1) /* I2C Data Port */

usr/src/uts/common/io/yge/yge.h

848

#define I2C_CLK BIT(0) /* I2C Clock Port */

usr/src/uts/common/io/yge/yge.h

855

#define BSC_START BIT(1) /* Start Blink Source Counter */

usr/src/uts/common/io/yge/yge.h

856

#define BSC_STOP BIT(0) /* Stop Blink Source Counter */

usr/src/uts/common/io/yge/yge.h

859

#define BSC_SRC BIT(0) /* Blink Source, 0=Off / 1=On */

usr/src/uts/common/io/yge/yge.h

862

#define BSC_T_ON BIT(2) /* Test mode on */

usr/src/uts/common/io/yge/yge.h

863

#define BSC_T_OFF BIT(1) /* Test mode off */

usr/src/uts/common/io/yge/yge.h

864

#define BSC_T_STEP BIT(0) /* Test step */

usr/src/uts/common/io/yge/yge.h

867

#define GLB_GPIO_CLK_DEB_ENA BIT(31) /* Clock Debug Enable */

usr/src/uts/common/io/yge/yge.h

873

#define GLB_GPIO_INT_RST_D3_DIS BIT(15)

usr/src/uts/common/io/yge/yge.h

874

#define GLB_GPIO_LED_PAD_SPEED_UP BIT(14) /* LED PAD Speed Up */

usr/src/uts/common/io/yge/yge.h

875

#define GLB_GPIO_STAT_RACE_DIS BIT(13) /* Status Race Disable */

usr/src/uts/common/io/yge/yge.h

878

#define GLB_GPIO_RAND_ENA BIT(10) /* Random Enable */

usr/src/uts/common/io/yge/yge.h

879

#define GLB_GPIO_RAND_BIT_1 BIT(9) /* Random Bit 1 */

usr/src/uts/common/io/yge/yge.h

884

#define PEX_RD_ACCESS BIT(31) /* Access Mode Read = 1, Write = 0 */

usr/src/uts/common/io/yge/yge.h

885

#define PEX_DB_ACCESS BIT(30) /* Access to debug register */

usr/src/uts/common/io/yge/yge.h

892

#define RI_CLR_RD_PERR BIT(9) /* Clear IRQ RAM Read Parity Err */

usr/src/uts/common/io/yge/yge.h

893

#define RI_CLR_WR_PERR BIT(8) /* Clear IRQ RAM Write Parity Err */

usr/src/uts/common/io/yge/yge.h

894

#define RI_RST_CLR BIT(1) /* Clear RAM Interface Reset */

usr/src/uts/common/io/yge/yge.h

895

#define RI_RST_SET BIT(0) /* Set RAM Interface Reset */

usr/src/uts/common/io/yge/yge.h

907

#define TXA_ENA_FSYNC BIT(7) /* Enable force of sync Tx queue */

usr/src/uts/common/io/yge/yge.h

908

#define TXA_DIS_FSYNC BIT(6) /* Disable force of sync Tx queue */

usr/src/uts/common/io/yge/yge.h

909

#define TXA_ENA_ALLOC BIT(5) /* Enable alloc of free bandwidth */

usr/src/uts/common/io/yge/yge.h

910

#define TXA_DIS_ALLOC BIT(4) /* Disable alloc of free bandwidth */

usr/src/uts/common/io/yge/yge.h

911

#define TXA_START_RC BIT(3) /* Start sync Rate Control */

usr/src/uts/common/io/yge/yge.h

912

#define TXA_STOP_RC BIT(2) /* Stop sync Rate Control */

usr/src/uts/common/io/yge/yge.h

913

#define TXA_ENA_ARB BIT(1) /* Enable Tx Arbiter */

usr/src/uts/common/io/yge/yge.h

914

#define TXA_DIS_ARB BIT(0) /* Disable Tx Arbiter */

usr/src/uts/common/io/yge/yge.h

917

#define TXA_INT_T_ON BIT(5) /* Tx Arb Interval Timer Test On */

usr/src/uts/common/io/yge/yge.h

918

#define TXA_INT_T_OFF BIT(4) /* Tx Arb Interval Timer Test Off */

usr/src/uts/common/io/yge/yge.h

919

#define TXA_INT_T_STEP BIT(3) /* Tx Arb Interval Timer Step */

usr/src/uts/common/io/yge/yge.h

920

#define TXA_LIM_T_ON BIT(2) /* Tx Arb Limit Timer Test On */

usr/src/uts/common/io/yge/yge.h

921

#define TXA_LIM_T_OFF BIT(1) /* Tx Arb Limit Timer Test Off */

usr/src/uts/common/io/yge/yge.h

922

#define TXA_LIM_T_STEP BIT(0) /* Tx Arb Limit Timer Step */

usr/src/uts/common/io/yge/yge.h

925

#define TXA_PRIO_XS BIT(0) /* sync queue has prio to send */

usr/src/uts/common/io/yge/yge.h

931

#define BMU_IDLE BIT(31) /* BMU Idle State */

usr/src/uts/common/io/yge/yge.h

932

#define BMU_RX_TCP_PKT BIT(30) /* Rx TCP Packet (when RSS Hash enab) */

usr/src/uts/common/io/yge/yge.h

933

#define BMU_RX_IP_PKT BIT(29) /* Rx IP Packet (when RSS Hash enab) */

usr/src/uts/common/io/yge/yge.h

934

#define BMU_ENA_RX_RSS_HASH BIT(15) /* Enable Rx RSS Hash */

usr/src/uts/common/io/yge/yge.h

935

#define BMU_DIS_RX_RSS_HASH BIT(14) /* Disable Rx RSS Hash */

usr/src/uts/common/io/yge/yge.h

936

#define BMU_ENA_RX_CHKSUM BIT(13) /* Enable Rx TCP/IP Checksum Check */

usr/src/uts/common/io/yge/yge.h

937

#define BMU_DIS_RX_CHKSUM BIT(12) /* Disable Rx TCP/IP Checksum Check */

usr/src/uts/common/io/yge/yge.h

938

#define BMU_CLR_IRQ_PAR BIT(11) /* Clear IRQ on Parity errors (Rx) */

usr/src/uts/common/io/yge/yge.h

939

#define BMU_CLR_IRQ_TCP BIT(11) /* Clear IRQ on TCP seg. error (Tx) */

usr/src/uts/common/io/yge/yge.h

940

#define BMU_CLR_IRQ_CHK BIT(10) /* Clear IRQ Check */

usr/src/uts/common/io/yge/yge.h

941

#define BMU_STOP BIT(9) /* Stop Rx/Tx Queue */

usr/src/uts/common/io/yge/yge.h

942

#define BMU_START BIT(8) /* Start Rx/Tx Queue */

usr/src/uts/common/io/yge/yge.h

943

#define BMU_FIFO_OP_ON BIT(7) /* FIFO Operational On */

usr/src/uts/common/io/yge/yge.h

944

#define BMU_FIFO_OP_OFF BIT(6) /* FIFO Operational Off */

usr/src/uts/common/io/yge/yge.h

945

#define BMU_FIFO_ENA BIT(5) /* Enable FIFO */

usr/src/uts/common/io/yge/yge.h

946

#define BMU_FIFO_RST BIT(4) /* Reset FIFO */

usr/src/uts/common/io/yge/yge.h

947

#define BMU_OP_ON BIT(3) /* BMU Operational On */

usr/src/uts/common/io/yge/yge.h

948

#define BMU_OP_OFF BIT(2) /* BMU Operational Off */

usr/src/uts/common/io/yge/yge.h

949

#define BMU_RST_CLR BIT(1) /* Clear BMU Reset (Enable) */

usr/src/uts/common/io/yge/yge.h

950

#define BMU_RST_SET BIT(0) /* Set BMU Reset */

usr/src/uts/common/io/yge/yge.h

958

#define BMU_TX_IPIDINCR_ON BIT(13) /* Enable IP ID Increment */

usr/src/uts/common/io/yge/yge.h

959

#define BMU_TX_IPIDINCR_OFF BIT(12) /* Disable IP ID Increment */

usr/src/uts/common/io/yge/yge.h

960

#define BMU_TX_CLR_IRQ_TCP BIT(11) /* Clear IRQ on TCP segm. len mism. */

usr/src/uts/common/io/yge/yge.h

964

#define F_TX_CHK_AUTO_OFF BIT(31) /* Tx csum auto-calc Off (Yukon EX) */

usr/src/uts/common/io/yge/yge.h

965

#define F_TX_CHK_AUTO_ON BIT(30) /* Tx csum auto-calc On (Yukon EX) */

usr/src/uts/common/io/yge/yge.h

966

#define F_ALM_FULL BIT(27) /* Rx FIFO: almost full */

usr/src/uts/common/io/yge/yge.h

967

#define F_EMPTY BIT(27) /* Tx FIFO: empty flag */

usr/src/uts/common/io/yge/yge.h

968

#define F_FIFO_EOF BIT(26) /* Tag (EOF Flag) bit in FIFO */

usr/src/uts/common/io/yge/yge.h

969

#define F_WM_REACHED BIT(25) /* Watermark reached */

usr/src/uts/common/io/yge/yge.h

970

#define F_M_RX_RAM_DIS BIT(24) /* MAC Rx RAM Read Port disable */

usr/src/uts/common/io/yge/yge.h

976

#define PREF_UNIT_OP_ON BIT(3) /* prefetch unit operational */

usr/src/uts/common/io/yge/yge.h

977

#define PREF_UNIT_OP_OFF BIT(2) /* prefetch unit not operational */

usr/src/uts/common/io/yge/yge.h

978

#define PREF_UNIT_RST_CLR BIT(1) /* Clear Prefetch Unit Reset */

usr/src/uts/common/io/yge/yge.h

979

#define PREF_UNIT_RST_SET BIT(0) /* Set Prefetch Unit Reset */

usr/src/uts/common/io/yge/yge.h

995

#define RB_PC_DEC BIT(3) /* Packet Counter Decrement */

usr/src/uts/common/io/yge/yge.h

996

#define RB_PC_T_ON BIT(2) /* Packet Counter Test On */

usr/src/uts/common/io/yge/yge.h

997

#define RB_PC_T_OFF BIT(1) /* Packet Counter Test Off */

usr/src/uts/common/io/yge/yge.h

998

#define RB_PC_INC BIT(0) /* Packet Counter Increment */

usr/src/uts/intel/io/dnet/dnet_mii.c

802

BIT(9, reg) ? "serial":"nibble");

usr/src/uts/intel/io/dnet/dnet_mii.c

805

BIT(reg, 5) ? "" : "no ",

usr/src/uts/intel/io/dnet/dnet_mii.c

806

BIT(reg, 4) ? "" : "no ",

usr/src/uts/intel/io/dnet/dnet_mii.c

807

BIT(reg, 3) ? "UTP" : "STP",

usr/src/uts/intel/io/dnet/dnet_mii.c

808

BIT(reg, 2) ? "low" : "normal",

usr/src/uts/intel/io/dnet/dnet_mii.c

809

BIT(reg, 0) ? "enabled" : "disabled");

usr/src/uts/intel/io/vmm/amd/amdvi_hw.c

149

#define PCIM_ATS_EN BIT(31)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

132

#define AMDVI_CMP_WAIT_STORE BIT(0) /* Write back data. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

133

#define AMDVI_CMP_WAIT_INTR BIT(1) /* Completion wait interrupt. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

134

#define AMDVI_CMP_WAIT_FLUSH BIT(2) /* Flush queue. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

137

#define AMDVI_INVD_PAGE_S BIT(0) /* Invalidation size. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

138

#define AMDVI_INVD_PAGE_PDE BIT(1) /* Invalidate PDE. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

139

#define AMDVI_INVD_PAGE_GN_GVA BIT(2) /* GPA or GVA. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

144

#define AMDVI_INVD_IOTLB_S BIT(0) /* Invalidation size 4k or addr */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

145

#define AMDVI_INVD_IOTLB_GN_GVA BIT(2) /* GPA or GVA. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

265

#define IVHD_FLAG_HTT BIT(0) /* Hypertransport Tunnel. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

266

#define IVHD_FLAG_PPW BIT(1) /* Pass posted write. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

267

#define IVHD_FLAG_RPPW BIT(2) /* Response pass posted write. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

268

#define IVHD_FLAG_ISOC BIT(3) /* Isoc support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

269

#define IVHD_FLAG_IOTLB BIT(4) /* IOTLB support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

270

#define IVHD_FLAG_COH BIT(5) /* Coherent control, default 1 */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

271

#define IVHD_FLAG_PFS BIT(6) /* Prefetch IOMMU pages. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

272

#define IVHD_FLAG_PPRS BIT(7) /* Peripheral page support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

275

#define IVHD_DEV_LINT0_PASS BIT(6) /* LINT0 interrupts. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

276

#define IVHD_DEV_LINT1_PASS BIT(7) /* LINT1 interrupts. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

279

#define IVHD_DEV_INIT_PASS BIT(0) /* INIT */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

280

#define IVHD_DEV_EXTINTR_PASS BIT(1) /* ExtInt */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

281

#define IVHD_DEV_NMI_PASS BIT(2) /* NMI */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

284

#define IVHD_DEV_EXT_ATS_DISABLE BIT(31) /* Disable ATS */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

287

#define AMDVI_CTRL_EN BIT(0) /* IOMMU enable. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

288

#define AMDVI_CTRL_HTT BIT(1) /* Hypertransport tunnel enable. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

289

#define AMDVI_CTRL_ELOG BIT(2) /* Event log enable. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

290

#define AMDVI_CTRL_ELOGINT BIT(3) /* Event log interrupt. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

291

#define AMDVI_CTRL_COMINT BIT(4) /* Completion wait interrupt. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

292

#define AMDVI_CTRL_PPW BIT(8)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

293

#define AMDVI_CTRL_RPPW BIT(9)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

294

#define AMDVI_CTRL_COH BIT(10)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

295

#define AMDVI_CTRL_ISOC BIT(11)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

296

#define AMDVI_CTRL_CMD BIT(12) /* Command buffer enable. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

297

#define AMDVI_CTRL_PPRLOG BIT(13)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

298

#define AMDVI_CTRL_PPRINT BIT(14)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

299

#define AMDVI_CTRL_PPREN BIT(15)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

300

#define AMDVI_CTRL_GTE BIT(16) /* Guest translation enable. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

301

#define AMDVI_CTRL_GAE BIT(17) /* Guest APIC enable. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

319

#define AMDVI_MAX_DOMAIN (BIT(16) - 1)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

324

#define AMDVI_PT_PRESENT BIT(0)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

325

#define AMDVI_PT_COHERENT BIT(60)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

326

#define AMDVI_PT_READ BIT(61)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

327

#define AMDVI_PT_WRITE BIT(62)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

337

#define AMDVI_STATUS_EV_OF BIT(0) /* Event overflow. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

338

#define AMDVI_STATUS_EV_INTR BIT(1) /* Event interrupt. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

340

#define AMDVI_STATUS_CMP BIT(2)

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

45

#define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

46

#define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

47

#define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

48

#define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

49

#define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

54

#define AMDVI_EX_FEA_PREFSUP BIT(0) /* Prefetch command support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

55

#define AMDVI_EX_FEA_PPRSUP BIT(1) /* PPR support */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

56

#define AMDVI_EX_FEA_XTSUP BIT(2) /* Reserved */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

57

#define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

58

#define AMDVI_EX_FEA_GTSUP BIT(4) /* Guest translation support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

59

#define AMDVI_EX_FEA_EFRW BIT(5) /* Reserved */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

60

#define AMDVI_EX_FEA_IASUP BIT(6) /* Invalidate all command supp. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

61

#define AMDVI_EX_FEA_GASUP BIT(7) /* Guest APIC or AVIC support. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

62

#define AMDVI_EX_FEA_HESUP BIT(8) /* Hardware Error. */

usr/src/uts/intel/io/vmm/amd/amdvi_priv.h

63

#define AMDVI_EX_FEA_PCSUP BIT(9) /* Performance counters support. */

usr/src/uts/intel/io/vmm/amd/svm.c

301

mask = (BIT(n) << 16) | BIT(n);

usr/src/uts/intel/io/vmm/amd/svm.c

327

svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(n));

usr/src/uts/intel/io/vmm/amd/svm.c

330

svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(IDT_MC));

usr/src/uts/intel/io/vmm/amd/svm.c

574

inout->flags |= (info1 & BIT(0)) ? INOUT_IN : 0;

usr/src/uts/intel/io/vmm/amd/svm.c

575

inout->flags |= (info1 & BIT(3)) ? INOUT_REP : 0;

usr/src/uts/intel/io/vmm/amd/svm.c

576

inout->flags |= (info1 & BIT(2)) ? INOUT_STR : 0;

usr/src/uts/intel/io/vmm/amd/svm.c

788

BIT(0) | BIT(16));

usr/src/uts/intel/io/vmm/amd/svm.c

800

BIT(0) | BIT(16));

usr/src/uts/intel/io/vmm/amd/vmcb.h

100

#define VMCB_INTCPT_VMMCALL BIT(1)

usr/src/uts/intel/io/vmm/amd/vmcb.h

101

#define VMCB_INTCPT_VMLOAD BIT(2)

usr/src/uts/intel/io/vmm/amd/vmcb.h

102

#define VMCB_INTCPT_VMSAVE BIT(3)

usr/src/uts/intel/io/vmm/amd/vmcb.h

103

#define VMCB_INTCPT_STGI BIT(4)

usr/src/uts/intel/io/vmm/amd/vmcb.h

104

#define VMCB_INTCPT_CLGI BIT(5)

usr/src/uts/intel/io/vmm/amd/vmcb.h

105

#define VMCB_INTCPT_SKINIT BIT(6)

usr/src/uts/intel/io/vmm/amd/vmcb.h

106

#define VMCB_INTCPT_RDTSCP BIT(7)

usr/src/uts/intel/io/vmm/amd/vmcb.h

107

#define VMCB_INTCPT_ICEBP BIT(8)

usr/src/uts/intel/io/vmm/amd/vmcb.h

108

#define VMCB_INTCPT_WBINVD BIT(9)

usr/src/uts/intel/io/vmm/amd/vmcb.h

109

#define VMCB_INTCPT_MONITOR BIT(10)

usr/src/uts/intel/io/vmm/amd/vmcb.h

110

#define VMCB_INTCPT_MWAIT BIT(11)

usr/src/uts/intel/io/vmm/amd/vmcb.h

111

#define VMCB_INTCPT_MWAIT_ARMED BIT(12)

usr/src/uts/intel/io/vmm/amd/vmcb.h

112

#define VMCB_INTCPT_XSETBV BIT(13)

usr/src/uts/intel/io/vmm/amd/vmcb.h

122

#define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */

usr/src/uts/intel/io/vmm/amd/vmcb.h

123

#define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */

usr/src/uts/intel/io/vmm/amd/vmcb.h

124

#define VMCB_CACHE_ASID BIT(2) /* ASID */

usr/src/uts/intel/io/vmm/amd/vmcb.h

125

#define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */

usr/src/uts/intel/io/vmm/amd/vmcb.h

126

#define VMCB_CACHE_NP BIT(4) /* Nested Paging */

usr/src/uts/intel/io/vmm/amd/vmcb.h

127

#define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */

usr/src/uts/intel/io/vmm/amd/vmcb.h

128

#define VMCB_CACHE_DR BIT(6) /* Debug registers */

usr/src/uts/intel/io/vmm/amd/vmcb.h

129

#define VMCB_CACHE_DT BIT(7) /* GDT/IDT */

usr/src/uts/intel/io/vmm/amd/vmcb.h

130

#define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */

usr/src/uts/intel/io/vmm/amd/vmcb.h

131

#define VMCB_CACHE_CR2 BIT(9) /* page fault address */

usr/src/uts/intel/io/vmm/amd/vmcb.h

132

#define VMCB_CACHE_LBR BIT(10) /* Last branch */

usr/src/uts/intel/io/vmm/amd/vmcb.h

135

#define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */

usr/src/uts/intel/io/vmm/amd/vmcb.h

136

#define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */

usr/src/uts/intel/io/vmm/amd/vmcb.h

194

#define VMCB_NPF_INFO1_P BIT(0) /* Nested page present. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

195

#define VMCB_NPF_INFO1_W BIT(1) /* Access was write. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

196

#define VMCB_NPF_INFO1_U BIT(2) /* Access was user access. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

197

#define VMCB_NPF_INFO1_RSV BIT(3) /* Reserved bits present. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

198

#define VMCB_NPF_INFO1_ID BIT(4) /* Code read. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

200

#define VMCB_NPF_INFO1_GPA BIT(32) /* Guest physical address. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

201

#define VMCB_NPF_INFO1_GPT BIT(33) /* Guest page table. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

209

#define VMCB_EXITINTINFO_EC_VALID(x) (((x) & BIT(11)) != 0)

usr/src/uts/intel/io/vmm/amd/vmcb.h

210

#define VMCB_EXITINTINFO_VALID(x) (((x) & BIT(31)) != 0)

usr/src/uts/intel/io/vmm/amd/vmcb.h

257

#define VMCB_CS_ATTRIB_L BIT(9) /* Long mode. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

258

#define VMCB_CS_ATTRIB_D BIT(10) /* OPerand size bit. */

usr/src/uts/intel/io/vmm/amd/vmcb.h

261

#define V_IRQ BIT(0) /* Offset 0x60 bit 8 (0x61 bit 0) */

usr/src/uts/intel/io/vmm/amd/vmcb.h

262

#define V_VGIF_VALUE BIT(1) /* Offset 0x60 bit 9 (0x61 bit 1) */

usr/src/uts/intel/io/vmm/amd/vmcb.h

266

#define V_IGN_TPR BIT(4) /* Offset 0x60 bit 20 (0x62 bit 4) */

usr/src/uts/intel/io/vmm/amd/vmcb.h

269

#define V_INTR_MASKING BIT(0) /* Offset 0x60 bit 24 (0x63 bit 0) */

usr/src/uts/intel/io/vmm/amd/vmcb.h

270

#define V_VGIF_ENABLE BIT(1) /* Offset 0x60 bit 25 (0x63 bit 1) */

usr/src/uts/intel/io/vmm/amd/vmcb.h

271

#define V_AVIC_ENABLE BIT(7) /* Offset 0x60 bit 31 (0x63 bit 7) */

usr/src/uts/intel/io/vmm/amd/vmcb.h

274

#define VIRTUAL_INTR_SHADOW BIT(0)

usr/src/uts/intel/io/vmm/amd/vmcb.h

275

#define GUEST_INTERRUPT_MASK BIT(1)

usr/src/uts/intel/io/vmm/amd/vmcb.h

278

#define NP_ENABLE BIT(0) /* Enable nested paging */

usr/src/uts/intel/io/vmm/amd/vmcb.h

279

#define SEV_ENABLE BIT(1) /* Enable SEV */

usr/src/uts/intel/io/vmm/amd/vmcb.h

280

#define SEV_ES_ENABLE BIT(2) /* Enable SEV-ES */

usr/src/uts/intel/io/vmm/amd/vmcb.h

281

#define GUEST_MODE_EXEC_TRAP BIT(3) /* Guest mode execute trap */

usr/src/uts/intel/io/vmm/amd/vmcb.h

282

#define VIRT_TRANSPAR_ENCRYPT BIT(5) /* Virtual transparent encryption */

usr/src/uts/intel/io/vmm/amd/vmcb.h

285

#define LBR_VIRT_ENABLE BIT(0) /* Enable LBR virtualization accel */

usr/src/uts/intel/io/vmm/amd/vmcb.h

286

#define VIRT_VMSAVE_VMLOAD BIT(1) /* Virtualized VMSAVE/VMLOAD */

usr/src/uts/intel/io/vmm/amd/vmcb.h

65

#define VMCB_INTCPT_INTR BIT(0)

usr/src/uts/intel/io/vmm/amd/vmcb.h

66

#define VMCB_INTCPT_NMI BIT(1)

usr/src/uts/intel/io/vmm/amd/vmcb.h

67

#define VMCB_INTCPT_SMI BIT(2)

usr/src/uts/intel/io/vmm/amd/vmcb.h

68

#define VMCB_INTCPT_INIT BIT(3)

usr/src/uts/intel/io/vmm/amd/vmcb.h

69

#define VMCB_INTCPT_VINTR BIT(4)

usr/src/uts/intel/io/vmm/amd/vmcb.h

70

#define VMCB_INTCPT_CR0_WRITE BIT(5)

usr/src/uts/intel/io/vmm/amd/vmcb.h

71

#define VMCB_INTCPT_IDTR_READ BIT(6)

usr/src/uts/intel/io/vmm/amd/vmcb.h

72

#define VMCB_INTCPT_GDTR_READ BIT(7)

usr/src/uts/intel/io/vmm/amd/vmcb.h

73

#define VMCB_INTCPT_LDTR_READ BIT(8)

usr/src/uts/intel/io/vmm/amd/vmcb.h

74

#define VMCB_INTCPT_TR_READ BIT(9)

usr/src/uts/intel/io/vmm/amd/vmcb.h

75

#define VMCB_INTCPT_IDTR_WRITE BIT(10)

usr/src/uts/intel/io/vmm/amd/vmcb.h

76

#define VMCB_INTCPT_GDTR_WRITE BIT(11)

usr/src/uts/intel/io/vmm/amd/vmcb.h

77

#define VMCB_INTCPT_LDTR_WRITE BIT(12)

usr/src/uts/intel/io/vmm/amd/vmcb.h

78

#define VMCB_INTCPT_TR_WRITE BIT(13)

usr/src/uts/intel/io/vmm/amd/vmcb.h

79

#define VMCB_INTCPT_RDTSC BIT(14)

usr/src/uts/intel/io/vmm/amd/vmcb.h

80

#define VMCB_INTCPT_RDPMC BIT(15)

usr/src/uts/intel/io/vmm/amd/vmcb.h

81

#define VMCB_INTCPT_PUSHF BIT(16)

usr/src/uts/intel/io/vmm/amd/vmcb.h

82

#define VMCB_INTCPT_POPF BIT(17)

usr/src/uts/intel/io/vmm/amd/vmcb.h

83

#define VMCB_INTCPT_CPUID BIT(18)

usr/src/uts/intel/io/vmm/amd/vmcb.h

84

#define VMCB_INTCPT_RSM BIT(19)

usr/src/uts/intel/io/vmm/amd/vmcb.h

85

#define VMCB_INTCPT_IRET BIT(20)

usr/src/uts/intel/io/vmm/amd/vmcb.h

86

#define VMCB_INTCPT_INTn BIT(21)

usr/src/uts/intel/io/vmm/amd/vmcb.h

87

#define VMCB_INTCPT_INVD BIT(22)

usr/src/uts/intel/io/vmm/amd/vmcb.h

88

#define VMCB_INTCPT_PAUSE BIT(23)

usr/src/uts/intel/io/vmm/amd/vmcb.h

89

#define VMCB_INTCPT_HLT BIT(24)

usr/src/uts/intel/io/vmm/amd/vmcb.h

90

#define VMCB_INTCPT_INVLPG BIT(25)

usr/src/uts/intel/io/vmm/amd/vmcb.h

91

#define VMCB_INTCPT_INVLPGA BIT(26)

usr/src/uts/intel/io/vmm/amd/vmcb.h

92

#define VMCB_INTCPT_IO BIT(27)

usr/src/uts/intel/io/vmm/amd/vmcb.h

93

#define VMCB_INTCPT_MSR BIT(28)

usr/src/uts/intel/io/vmm/amd/vmcb.h

94

#define VMCB_INTCPT_TASK_SWITCH BIT(29)

usr/src/uts/intel/io/vmm/amd/vmcb.h

95

#define VMCB_INTCPT_FERR_FREEZE BIT(30)

usr/src/uts/intel/io/vmm/amd/vmcb.h

96

#define VMCB_INTCPT_SHUTDOWN BIT(31)

usr/src/uts/intel/io/vmm/amd/vmcb.h

99

#define VMCB_INTCPT_VMRUN BIT(0)