RT2661_WRITE
RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
RT2661_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
RT2661_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
RT2661_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
RT2661_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << 0);
RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x3);
RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x150);
RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0xf);
RT2661_WRITE(sc, RT2661_MAC_CSR4, tmp);
RT2661_WRITE(sc, RT2661_MAC_CSR5, tmp);
RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp);
RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_MAC_CSR2, tmp);
RT2661_WRITE(sc, RT2661_MAC_CSR3, tmp);
RT2661_WRITE(sc, RT2661_PHY_CSR3, val);
RT2661_WRITE(sc, RT2661_PHY_CSR3, tmp);
RT2661_WRITE(sc, RT2661_PHY_CSR0, tmp);
RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
RT2661_WRITE(sc, RT2661_PHY_CSR4, tmp);
RT2661_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].paddr);
RT2661_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].paddr);
RT2661_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].paddr);
RT2661_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].paddr);
RT2661_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.paddr);
RT2661_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.paddr);
RT2661_WRITE(sc, RT2661_TX_RING_CSR0,
RT2661_WRITE(sc, RT2661_TX_RING_CSR1,
RT2661_WRITE(sc, RT2661_RX_RING_CSR,
RT2661_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
RT2661_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
RT2661_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
RT2661_WRITE(sc, RT2661_MAC_CSR1, 4);
RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR,
RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
RT2661_WRITE((sc), RT2661_E2PROM_CSR, (val)); \