REG_WR_IND
REG_WR_IND(pdev, cpu_reg->mode, val);
REG_WR_IND(pdev, cpu_reg->state, cpu_reg->state_value_clear);
REG_WR_IND(pdev, cpu_reg->inst, 0);
REG_WR_IND(pdev, cpu_reg->pc, fw->start_addr);
REG_WR_IND(pdev, cpu_reg->state, cpu_reg->state_value_clear);
REG_WR_IND(pdev, cpu_reg->mode, val);
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(pdev, OFFSETOF(reg_space_t, cp.cp_scratch[0])+CP_HSI_OFFSETOFF(fw_doorbell), 1);
REG_WR_IND(pdev, OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(fw_doorbell), 1);
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_fw_buf_free), val);
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(pdev, 0xe0024, val);
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(
REG_WR_IND(pdev, offset, DRV_ACK_CAP_SIGNATURE |
REG_WR_IND(lmdevice, (OFFSETOF(reg_space_t, tpat.tpat_scratch[0]) +
REG_WR_IND(lmdevice, offset, msg_code);
REG_WR_IND(pdev,rq_onchip_at_reg+temp*8,0);
REG_WR_IND(pdev,rq_onchip_at_reg+temp*8+4,on_chip_addr2_val);
REG_WR_IND( pdev, offset, val_32[0] );
REG_WR_IND( pdev, offset+4, val_32[1] );
REG_WR_IND(pdev,rq_onchip_at_reg+temp*8,ONCHIP_ADDR1(addr_table[k][i].as_u64));
REG_WR_IND(pdev,rq_onchip_at_reg+temp*8+4,ONCHIP_ADDR2(addr_table[k][i].as_u64));
REG_WR_IND(pdev,QM_REG_PTRTBL +8*i ,0);
REG_WR_IND(pdev,QM_REG_PTRTBL +8*i +4 ,0);
REG_WR_IND(pdev,QM_REG_PTRTBL_EXT_A +8*i ,0);
REG_WR_IND(pdev,QM_REG_PTRTBL_EXT_A +8*i +4 ,0);
REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_FIRSTFREE1 : SRC_REG_FIRSTFREE0),pdev->vars.searcher_t2_phys_addr_table[0].as_u32.low);
REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_FIRSTFREE1 : SRC_REG_FIRSTFREE0)+4,pdev->vars.searcher_t2_phys_addr_table[0].as_u32.high);
REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_LASTFREE1 : SRC_REG_LASTFREE0),src_addr.as_u32.low);
REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_LASTFREE1 : SRC_REG_LASTFREE0)+4,src_addr.as_u32.high);
REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB, wb_write[0]);
REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+4,wb_write[1]);
REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+8,wb_write[2]);
REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB, wb_write[0]);
REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+4,wb_write[1]);
REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+8,wb_write[2]);
REG_WR_IND( pdev, reg_be+val, val_32[0] ) ;
REG_WR_IND( pdev, reg_be+val+4, val_32[1] ) ;