Symbol: REG_WRITE
usr/src/uts/common/io/arn/arn_ani.c
279
REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
usr/src/uts/common/io/arn/arn_ani.c
280
REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
usr/src/uts/common/io/arn/arn_ani.c
281
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
usr/src/uts/common/io/arn/arn_ani.c
282
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
usr/src/uts/common/io/arn/arn_ani.c
564
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
usr/src/uts/common/io/arn/arn_ani.c
565
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
usr/src/uts/common/io/arn/arn_ani.c
612
REG_WRITE(ah, AR_PHY_ERR_1,
usr/src/uts/common/io/arn/arn_ani.c
614
REG_WRITE(ah, AR_PHY_ERR_MASK_1,
usr/src/uts/common/io/arn/arn_ani.c
623
REG_WRITE(ah, AR_PHY_ERR_2,
usr/src/uts/common/io/arn/arn_ani.c
625
REG_WRITE(ah, AR_PHY_ERR_MASK_2,
usr/src/uts/common/io/arn/arn_ani.c
683
REG_WRITE(ah, AR_FILT_OFDM, 0);
usr/src/uts/common/io/arn/arn_ani.c
684
REG_WRITE(ah, AR_FILT_CCK, 0);
usr/src/uts/common/io/arn/arn_ani.c
685
REG_WRITE(ah, AR_MIBC,
usr/src/uts/common/io/arn/arn_ani.c
687
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
usr/src/uts/common/io/arn/arn_ani.c
688
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
usr/src/uts/common/io/arn/arn_ani.c
700
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
usr/src/uts/common/io/arn/arn_ani.c
704
REG_WRITE(ah, AR_FILT_OFDM, 0);
usr/src/uts/common/io/arn/arn_ani.c
705
REG_WRITE(ah, AR_FILT_CCK, 0);
usr/src/uts/common/io/arn/arn_ani.c
761
REG_WRITE(ah, AR_FILT_OFDM, 0);
usr/src/uts/common/io/arn/arn_ani.c
762
REG_WRITE(ah, AR_FILT_CCK, 0);
usr/src/uts/common/io/arn/arn_ani.c
764
REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
usr/src/uts/common/io/arn/arn_ani.c
869
REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
usr/src/uts/common/io/arn/arn_ani.c
870
REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
usr/src/uts/common/io/arn/arn_ani.c
888
REG_WRITE(ah, AR_PHY_ERR_1, 0);
usr/src/uts/common/io/arn/arn_ani.c
889
REG_WRITE(ah, AR_PHY_ERR_2, 0);
usr/src/uts/common/io/arn/arn_ath9k.h
621
REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
usr/src/uts/common/io/arn/arn_ath9k.h
623
REG_WRITE(_a, _r, \
usr/src/uts/common/io/arn/arn_ath9k.h
626
REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
usr/src/uts/common/io/arn/arn_ath9k.h
628
REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
usr/src/uts/common/io/arn/arn_calib.c
221
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
usr/src/uts/common/io/arn/arn_calib.c
227
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
usr/src/uts/common/io/arn/arn_calib.c
232
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
usr/src/uts/common/io/arn/arn_calib.c
237
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
usr/src/uts/common/io/arn/arn_calib.c
534
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
usr/src/uts/common/io/arn/arn_calib.c
541
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
usr/src/uts/common/io/arn/arn_calib.c
594
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
usr/src/uts/common/io/arn/arn_calib.c
600
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
usr/src/uts/common/io/arn/arn_calib.c
694
REG_WRITE(ah, ar5416_cca_regs[i], val);
usr/src/uts/common/io/arn/arn_calib.c
716
REG_WRITE(ah, ar5416_cca_regs[i], val);
usr/src/uts/common/io/arn/arn_calib.c
876
REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
usr/src/uts/common/io/arn/arn_calib.c
885
REG_WRITE(ah, 0x7834, regVal);
usr/src/uts/common/io/arn/arn_calib.c
888
REG_WRITE(ah, 0x9808, regVal);
usr/src/uts/common/io/arn/arn_calib.c
905
REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
usr/src/uts/common/io/arn/arn_calib.c
913
REG_WRITE(ah, 0x7834, regVal);
usr/src/uts/common/io/arn/arn_calib.c
919
REG_WRITE(ah, 0x7834, regVal);
usr/src/uts/common/io/arn/arn_calib.c
939
REG_WRITE(ah, 0x7834, regVal);
usr/src/uts/common/io/arn/arn_calib.c
942
REG_WRITE(ah, 0x9808, regVal);
usr/src/uts/common/io/arn/arn_calib.c
945
REG_WRITE(ah, regList[i][0], regList[i][1]);
usr/src/uts/common/io/arn/arn_calib.c
950
REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
usr/src/uts/common/io/arn/arn_calib.c
961
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
usr/src/uts/common/io/arn/arn_calib.c
975
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
usr/src/uts/common/io/arn/arn_eeprom.c
1108
REG_WRITE(ah,
usr/src/uts/common/io/arn/arn_eeprom.c
1128
REG_WRITE(ah, regOffset, reg32);
usr/src/uts/common/io/arn/arn_eeprom.c
1225
REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
usr/src/uts/common/io/arn/arn_eeprom.c
1244
REG_WRITE(ah, regOffset, reg32);
usr/src/uts/common/io/arn/arn_eeprom.c
1865
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
usr/src/uts/common/io/arn/arn_eeprom.c
1870
REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
usr/src/uts/common/io/arn/arn_eeprom.c
1877
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
usr/src/uts/common/io/arn/arn_eeprom.c
1882
REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
usr/src/uts/common/io/arn/arn_eeprom.c
1889
REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
usr/src/uts/common/io/arn/arn_eeprom.c
1894
REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
usr/src/uts/common/io/arn/arn_eeprom.c
1901
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
usr/src/uts/common/io/arn/arn_eeprom.c
1910
REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
usr/src/uts/common/io/arn/arn_eeprom.c
1920
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
usr/src/uts/common/io/arn/arn_eeprom.c
1927
REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
usr/src/uts/common/io/arn/arn_eeprom.c
1998
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
usr/src/uts/common/io/arn/arn_eeprom.c
2003
REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
usr/src/uts/common/io/arn/arn_eeprom.c
2010
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
usr/src/uts/common/io/arn/arn_eeprom.c
2015
REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
usr/src/uts/common/io/arn/arn_eeprom.c
2022
REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
usr/src/uts/common/io/arn/arn_eeprom.c
2027
REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
usr/src/uts/common/io/arn/arn_eeprom.c
2034
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
usr/src/uts/common/io/arn/arn_eeprom.c
2044
REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
usr/src/uts/common/io/arn/arn_eeprom.c
2054
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
usr/src/uts/common/io/arn/arn_eeprom.c
2212
REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
usr/src/uts/common/io/arn/arn_eeprom.c
2227
REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
usr/src/uts/common/io/arn/arn_eeprom.c
2230
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
usr/src/uts/common/io/arn/arn_eeprom.c
2270
REG_WRITE(ah,
usr/src/uts/common/io/arn/arn_eeprom.c
2280
REG_WRITE(ah,
usr/src/uts/common/io/arn/arn_eeprom.c
2303
REG_WRITE(ah,
usr/src/uts/common/io/arn/arn_eeprom.c
2311
REG_WRITE(ah,
usr/src/uts/common/io/arn/arn_eeprom.c
2386
REG_WRITE(ah, AR_PHY_RF_CTL4,
usr/src/uts/common/io/arn/arn_eeprom.c
2448
REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
usr/src/uts/common/io/arn/arn_eeprom.c
2451
REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
usr/src/uts/common/io/arn/arn_eeprom.c
2454
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
usr/src/uts/common/io/arn/arn_eeprom.c
2481
REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
usr/src/uts/common/io/arn/arn_eeprom.c
2494
REG_WRITE(ah, 0x99ac, regVal);
usr/src/uts/common/io/arn/arn_eeprom.c
2499
REG_WRITE(ah, 0xa208, regVal);
usr/src/uts/common/io/arn/arn_eeprom.c
2578
REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
usr/src/uts/common/io/arn/arn_eeprom.c
2585
REG_WRITE(ah, AR_PHY_RF_CTL4,
usr/src/uts/common/io/arn/arn_eeprom.c
69
REG_WRITE(ah, reg, regVal);
usr/src/uts/common/io/arn/arn_hw.c
1050
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
usr/src/uts/common/io/arn/arn_hw.c
1058
REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
usr/src/uts/common/io/arn/arn_hw.c
1059
REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
usr/src/uts/common/io/arn/arn_hw.c
1061
REG_WRITE(ah, AR_QOS_NO_ACK,
usr/src/uts/common/io/arn/arn_hw.c
1066
REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
usr/src/uts/common/io/arn/arn_hw.c
1067
REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
usr/src/uts/common/io/arn/arn_hw.c
1068
REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
usr/src/uts/common/io/arn/arn_hw.c
1069
REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
usr/src/uts/common/io/arn/arn_hw.c
1070
REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
usr/src/uts/common/io/arn/arn_hw.c
1134
REG_WRITE(ah, (uint16_t)(AR_RTC_PLL_CONTROL), pll);
usr/src/uts/common/io/arn/arn_hw.c
1138
REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
usr/src/uts/common/io/arn/arn_hw.c
1157
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
usr/src/uts/common/io/arn/arn_hw.c
1158
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
usr/src/uts/common/io/arn/arn_hw.c
1165
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
usr/src/uts/common/io/arn/arn_hw.c
1166
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
usr/src/uts/common/io/arn/arn_hw.c
1172
REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
usr/src/uts/common/io/arn/arn_hw.c
1178
REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
usr/src/uts/common/io/arn/arn_hw.c
1203
REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
usr/src/uts/common/io/arn/arn_hw.c
1204
REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
usr/src/uts/common/io/arn/arn_hw.c
1207
REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
usr/src/uts/common/io/arn/arn_hw.c
1208
REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
usr/src/uts/common/io/arn/arn_hw.c
1209
REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
usr/src/uts/common/io/arn/arn_hw.c
1279
REG_WRITE(ah, AR_PCU_MISC,
usr/src/uts/common/io/arn/arn_hw.c
1350
REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
usr/src/uts/common/io/arn/arn_hw.c
1445
REG_WRITE(ah, AR_PHY(0), 0x00000007);
usr/src/uts/common/io/arn/arn_hw.c
1447
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
usr/src/uts/common/io/arn/arn_hw.c
1473
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
usr/src/uts/common/io/arn/arn_hw.c
1479
REG_WRITE(ah, reg, val);
usr/src/uts/common/io/arn/arn_hw.c
1506
REG_WRITE(ah, reg, val);
usr/src/uts/common/io/arn/arn_hw.c
1573
REG_WRITE(ah, AR_PHY_MODE, rfMode);
usr/src/uts/common/io/arn/arn_hw.c
1579
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
usr/src/uts/common/io/arn/arn_hw.c
1588
REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
usr/src/uts/common/io/arn/arn_hw.c
1591
REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
usr/src/uts/common/io/arn/arn_hw.c
1596
REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
usr/src/uts/common/io/arn/arn_hw.c
1598
REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
usr/src/uts/common/io/arn/arn_hw.c
1601
REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
usr/src/uts/common/io/arn/arn_hw.c
1604
REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
usr/src/uts/common/io/arn/arn_hw.c
1618
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
usr/src/uts/common/io/arn/arn_hw.c
1623
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
usr/src/uts/common/io/arn/arn_hw.c
1629
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
usr/src/uts/common/io/arn/arn_hw.c
1696
REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
usr/src/uts/common/io/arn/arn_hw.c
1707
REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
usr/src/uts/common/io/arn/arn_hw.c
1708
REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
usr/src/uts/common/io/arn/arn_hw.c
1710
REG_WRITE(ah, AR_RC, AR_RC_AHB);
usr/src/uts/common/io/arn/arn_hw.c
1718
REG_WRITE(ah, (uint16_t)(AR_RTC_RC), rst_flags);
usr/src/uts/common/io/arn/arn_hw.c
1721
REG_WRITE(ah, (uint16_t)(AR_RTC_RC), 0);
usr/src/uts/common/io/arn/arn_hw.c
1730
REG_WRITE(ah, AR_RC, 0);
usr/src/uts/common/io/arn/arn_hw.c
1743
REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
usr/src/uts/common/io/arn/arn_hw.c
1746
REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 0);
usr/src/uts/common/io/arn/arn_hw.c
1747
REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 1);
usr/src/uts/common/io/arn/arn_hw.c
1768
REG_WRITE(ah, AR_RTC_FORCE_WAKE,
usr/src/uts/common/io/arn/arn_hw.c
1807
REG_WRITE(ah, AR_PHY_TURBO, phymode);
usr/src/uts/common/io/arn/arn_hw.c
1811
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
usr/src/uts/common/io/arn/arn_hw.c
1812
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
usr/src/uts/common/io/arn/arn_hw.c
1878
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
usr/src/uts/common/io/arn/arn_hw.c
1924
REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
usr/src/uts/common/io/arn/arn_hw.c
2018
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
usr/src/uts/common/io/arn/arn_hw.c
2025
REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
usr/src/uts/common/io/arn/arn_hw.c
2055
REG_WRITE(ah, AR_PHY_TIMING11, newVal);
usr/src/uts/common/io/arn/arn_hw.c
2058
REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
usr/src/uts/common/io/arn/arn_hw.c
2076
REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
usr/src/uts/common/io/arn/arn_hw.c
2077
REG_WRITE(ah, chan_mask_reg[i], chan_mask);
usr/src/uts/common/io/arn/arn_hw.c
2110
REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2111
REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2121
REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2122
REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2132
REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2133
REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2143
REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2144
REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2154
REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2155
REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2165
REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2166
REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2176
REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2177
REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2187
REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2188
REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2242
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
usr/src/uts/common/io/arn/arn_hw.c
2249
REG_WRITE(ah, AR_PHY_SPUR_REG, new);
usr/src/uts/common/io/arn/arn_hw.c
2260
REG_WRITE(ah, AR_PHY_TIMING11, new);
usr/src/uts/common/io/arn/arn_hw.c
2278
REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
usr/src/uts/common/io/arn/arn_hw.c
2279
REG_WRITE(ah, chan_mask_reg[i], chan_mask);
usr/src/uts/common/io/arn/arn_hw.c
2312
REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2313
REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2323
REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2324
REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2334
REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2335
REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2345
REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2346
REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2356
REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2357
REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2367
REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2368
REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2378
REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2379
REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2389
REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2390
REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
usr/src/uts/common/io/arn/arn_hw.c
2505
REG_WRITE(ah, AR_STA_ID0, ARN_LE_READ_32(ahp->ah_macaddr));
usr/src/uts/common/io/arn/arn_hw.c
2506
REG_WRITE(ah, AR_STA_ID1, ARN_LE_READ_16(ahp->ah_macaddr + 4) |
usr/src/uts/common/io/arn/arn_hw.c
2513
REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
usr/src/uts/common/io/arn/arn_hw.c
2514
REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
usr/src/uts/common/io/arn/arn_hw.c
2516
REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
usr/src/uts/common/io/arn/arn_hw.c
2518
REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
usr/src/uts/common/io/arn/arn_hw.c
2519
REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
usr/src/uts/common/io/arn/arn_hw.c
2522
REG_WRITE(ah, AR_ISR, ~0);
usr/src/uts/common/io/arn/arn_hw.c
2524
REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
usr/src/uts/common/io/arn/arn_hw.c
2544
REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
usr/src/uts/common/io/arn/arn_hw.c
2559
REG_WRITE(ah, AR_STA_ID1,
usr/src/uts/common/io/arn/arn_hw.c
2564
REG_WRITE(ah, AR_OBS, 8);
usr/src/uts/common/io/arn/arn_hw.c
2581
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
usr/src/uts/common/io/arn/arn_hw.c
2582
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
usr/src/uts/common/io/arn/arn_hw.c
2585
REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
usr/src/uts/common/io/arn/arn_hw.c
2597
REG_WRITE(ah, AR_CFG, mask);
usr/src/uts/common/io/arn/arn_hw.c
2606
REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
usr/src/uts/common/io/arn/arn_hw.c
2633
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2634
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2635
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2636
REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2637
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2638
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
usr/src/uts/common/io/arn/arn_hw.c
2639
REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2640
REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2646
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2647
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2648
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2649
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2682
REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
usr/src/uts/common/io/arn/arn_hw.c
2683
REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
usr/src/uts/common/io/arn/arn_hw.c
2766
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
usr/src/uts/common/io/arn/arn_hw.c
2767
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
usr/src/uts/common/io/arn/arn_hw.c
2768
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
usr/src/uts/common/io/arn/arn_hw.c
2769
REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
usr/src/uts/common/io/arn/arn_hw.c
2770
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
usr/src/uts/common/io/arn/arn_hw.c
2771
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
usr/src/uts/common/io/arn/arn_hw.c
2781
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
usr/src/uts/common/io/arn/arn_hw.c
2782
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
usr/src/uts/common/io/arn/arn_hw.c
2783
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
usr/src/uts/common/io/arn/arn_hw.c
2784
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
usr/src/uts/common/io/arn/arn_hw.c
2785
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
usr/src/uts/common/io/arn/arn_hw.c
2786
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
usr/src/uts/common/io/arn/arn_hw.c
2793
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
usr/src/uts/common/io/arn/arn_hw.c
2794
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2795
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
usr/src/uts/common/io/arn/arn_hw.c
2796
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2797
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2798
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
usr/src/uts/common/io/arn/arn_hw.c
2801
REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2802
REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
usr/src/uts/common/io/arn/arn_hw.c
2803
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
usr/src/uts/common/io/arn/arn_hw.c
2804
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
usr/src/uts/common/io/arn/arn_hw.c
2806
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
usr/src/uts/common/io/arn/arn_hw.c
2807
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
usr/src/uts/common/io/arn/arn_hw.c
2808
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
usr/src/uts/common/io/arn/arn_hw.c
2809
REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
usr/src/uts/common/io/arn/arn_hw.c
2810
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
usr/src/uts/common/io/arn/arn_hw.c
2811
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
usr/src/uts/common/io/arn/arn_hw.c
2843
REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
usr/src/uts/common/io/arn/arn_hw.c
2858
REG_WRITE(ah, AR_RTC_FORCE_WAKE,
usr/src/uts/common/io/arn/arn_hw.c
2967
REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
usr/src/uts/common/io/arn/arn_hw.c
2973
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
usr/src/uts/common/io/arn/arn_hw.c
2974
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
usr/src/uts/common/io/arn/arn_hw.c
2976
REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
usr/src/uts/common/io/arn/arn_hw.c
2977
REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
usr/src/uts/common/io/arn/arn_hw.c
2978
REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
usr/src/uts/common/io/arn/arn_hw.c
2981
REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
usr/src/uts/common/io/arn/arn_hw.c
2983
REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
usr/src/uts/common/io/arn/arn_hw.c
2985
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
usr/src/uts/common/io/arn/arn_hw.c
2986
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
usr/src/uts/common/io/arn/arn_hw.c
2987
REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
usr/src/uts/common/io/arn/arn_hw.c
2989
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
usr/src/uts/common/io/arn/arn_hw.c
2993
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
usr/src/uts/common/io/arn/arn_hw.c
2994
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
usr/src/uts/common/io/arn/arn_hw.c
2995
REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
usr/src/uts/common/io/arn/arn_hw.c
2996
REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
usr/src/uts/common/io/arn/arn_hw.c
2997
REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
usr/src/uts/common/io/arn/arn_hw.c
2998
REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
usr/src/uts/common/io/arn/arn_hw.c
2999
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
usr/src/uts/common/io/arn/arn_hw.c
3000
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
usr/src/uts/common/io/arn/arn_hw.c
3001
REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
usr/src/uts/common/io/arn/arn_hw.c
3002
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
usr/src/uts/common/io/arn/arn_hw.c
3008
REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
usr/src/uts/common/io/arn/arn_hw.c
3011
REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
usr/src/uts/common/io/arn/arn_hw.c
3013
REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
usr/src/uts/common/io/arn/arn_hw.c
3015
REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
usr/src/uts/common/io/arn/arn_hw.c
3162
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
usr/src/uts/common/io/arn/arn_hw.c
3163
REG_WRITE(ah, AR_RC, 0);
usr/src/uts/common/io/arn/arn_hw.c
3172
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
usr/src/uts/common/io/arn/arn_hw.c
3202
REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
usr/src/uts/common/io/arn/arn_hw.c
3205
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
usr/src/uts/common/io/arn/arn_hw.c
3208
REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
usr/src/uts/common/io/arn/arn_hw.c
3256
REG_WRITE(ah, AR_IMR, mask);
usr/src/uts/common/io/arn/arn_hw.c
3266
REG_WRITE(ah, AR_IMR_S2, mask | mask2);
usr/src/uts/common/io/arn/arn_hw.c
3277
REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
usr/src/uts/common/io/arn/arn_hw.c
3279
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
usr/src/uts/common/io/arn/arn_hw.c
328
REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
usr/src/uts/common/io/arn/arn_hw.c
3281
REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
usr/src/uts/common/io/arn/arn_hw.c
3284
REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
usr/src/uts/common/io/arn/arn_hw.c
3286
REG_WRITE(ah, AR_INTR_SYNC_MASK,
usr/src/uts/common/io/arn/arn_hw.c
3309
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
usr/src/uts/common/io/arn/arn_hw.c
331
REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
usr/src/uts/common/io/arn/arn_hw.c
3310
REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
usr/src/uts/common/io/arn/arn_hw.c
3311
REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
usr/src/uts/common/io/arn/arn_hw.c
3317
REG_WRITE(ah, AR_NEXT_NDP_TIMER,
usr/src/uts/common/io/arn/arn_hw.c
3324
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
usr/src/uts/common/io/arn/arn_hw.c
3325
REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
usr/src/uts/common/io/arn/arn_hw.c
3329
REG_WRITE(ah, AR_NEXT_SWBA,
usr/src/uts/common/io/arn/arn_hw.c
3343
REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
usr/src/uts/common/io/arn/arn_hw.c
3344
REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
usr/src/uts/common/io/arn/arn_hw.c
3345
REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
usr/src/uts/common/io/arn/arn_hw.c
3346
REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
usr/src/uts/common/io/arn/arn_hw.c
3364
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
usr/src/uts/common/io/arn/arn_hw.c
3366
REG_WRITE(ah, AR_BEACON_PERIOD,
usr/src/uts/common/io/arn/arn_hw.c
3368
REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
usr/src/uts/common/io/arn/arn_hw.c
3397
REG_WRITE(ah, AR_NEXT_DTIM,
usr/src/uts/common/io/arn/arn_hw.c
3399
REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
usr/src/uts/common/io/arn/arn_hw.c
3401
REG_WRITE(ah, AR_SLEEP1,
usr/src/uts/common/io/arn/arn_hw.c
3410
REG_WRITE(ah, AR_SLEEP2,
usr/src/uts/common/io/arn/arn_hw.c
3413
REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
usr/src/uts/common/io/arn/arn_hw.c
3414
REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
usr/src/uts/common/io/arn/arn_hw.c
3422
REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
usr/src/uts/common/io/arn/arn_hw.c
346
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
usr/src/uts/common/io/arn/arn_hw.c
347
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
usr/src/uts/common/io/arn/arn_hw.c
348
REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
usr/src/uts/common/io/arn/arn_hw.c
349
REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
usr/src/uts/common/io/arn/arn_hw.c
350
REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
usr/src/uts/common/io/arn/arn_hw.c
351
REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
usr/src/uts/common/io/arn/arn_hw.c
352
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
usr/src/uts/common/io/arn/arn_hw.c
353
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
usr/src/uts/common/io/arn/arn_hw.c
354
REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
usr/src/uts/common/io/arn/arn_hw.c
356
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
usr/src/uts/common/io/arn/arn_hw.c
3734
REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
usr/src/uts/common/io/arn/arn_hw.c
375
REG_WRITE(ah, addr, wrData);
usr/src/uts/common/io/arn/arn_hw.c
3780
REG_WRITE(ah, addr, tmp);
usr/src/uts/common/io/arn/arn_hw.c
3867
REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
usr/src/uts/common/io/arn/arn_hw.c
3884
REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
usr/src/uts/common/io/arn/arn_hw.c
389
REG_WRITE(ah, addr, wrData);
usr/src/uts/common/io/arn/arn_hw.c
3956
REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
usr/src/uts/common/io/arn/arn_hw.c
3963
REG_WRITE(ah, AR_PHY_ERR, phybits);
usr/src/uts/common/io/arn/arn_hw.c
3966
REG_WRITE(ah, AR_RXCFG,
usr/src/uts/common/io/arn/arn_hw.c
3969
REG_WRITE(ah, AR_RXCFG,
usr/src/uts/common/io/arn/arn_hw.c
401
REG_WRITE(ah, regAddr[i], regHold[i]);
usr/src/uts/common/io/arn/arn_hw.c
4034
REG_WRITE(ah, AR_MCAST_FIL0, filter0);
usr/src/uts/common/io/arn/arn_hw.c
4035
REG_WRITE(ah, AR_MCAST_FIL1, filter1);
usr/src/uts/common/io/arn/arn_hw.c
4053
REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
usr/src/uts/common/io/arn/arn_hw.c
4054
REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
usr/src/uts/common/io/arn/arn_hw.c
4068
REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
usr/src/uts/common/io/arn/arn_hw.c
4069
REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
usr/src/uts/common/io/arn/arn_hw.c
4101
REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
usr/src/uts/common/io/arn/arn_hw.c
4129
REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
usr/src/uts/common/io/arn/arn_hw.c
4146
REG_WRITE(ah, AR_2040_MODE, macmode);
usr/src/uts/common/io/arn/arn_hw.c
562
REG_WRITE(ah, AR_PHY(0), 0x00000007);
usr/src/uts/common/io/arn/arn_hw.h
988
REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
usr/src/uts/common/io/arn/arn_mac.c
1066
REG_WRITE(ah, AR_RXDP, rxdp);
usr/src/uts/common/io/arn/arn_mac.c
1072
REG_WRITE(ah, AR_CR, AR_CR_RXE);
usr/src/uts/common/io/arn/arn_mac.c
1096
REG_WRITE(ah, AR_CR, AR_CR_RXD);
usr/src/uts/common/io/arn/arn_mac.c
134
REG_WRITE(ah, AR_QTXDP(q), txdp);
usr/src/uts/common/io/arn/arn_mac.c
145
REG_WRITE(ah, AR_Q_TXE, 1 << q);
usr/src/uts/common/io/arn/arn_mac.c
187
REG_WRITE(ah, AR_TXCFG,
usr/src/uts/common/io/arn/arn_mac.c
202
REG_WRITE(ah, AR_Q_TXD, 1 << q);
usr/src/uts/common/io/arn/arn_mac.c
217
REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
usr/src/uts/common/io/arn/arn_mac.c
218
REG_WRITE(ah, AR_QUIET_PERIOD, 100);
usr/src/uts/common/io/arn/arn_mac.c
219
REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
usr/src/uts/common/io/arn/arn_mac.c
251
REG_WRITE(ah, AR_Q_TXD, 0);
usr/src/uts/common/io/arn/arn_mac.c
42
REG_WRITE(ah, AR_IMR_S0,
usr/src/uts/common/io/arn/arn_mac.c
45
REG_WRITE(ah, AR_IMR_S1,
usr/src/uts/common/io/arn/arn_mac.c
60
REG_WRITE(ah, AR_MACMISC,
usr/src/uts/common/io/arn/arn_mac.c
823
REG_WRITE(ah, AR_DLCL_IFS(q),
usr/src/uts/common/io/arn/arn_mac.c
828
REG_WRITE(ah, AR_DRETRY_LIMIT(q),
usr/src/uts/common/io/arn/arn_mac.c
833
REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
usr/src/uts/common/io/arn/arn_mac.c
834
REG_WRITE(ah, AR_DMISC(q),
usr/src/uts/common/io/arn/arn_mac.c
838
REG_WRITE(ah, AR_QCBRCFG(q),
usr/src/uts/common/io/arn/arn_mac.c
841
REG_WRITE(ah, AR_QMISC(q),
usr/src/uts/common/io/arn/arn_mac.c
847
REG_WRITE(ah, AR_QRDYTIMECFG(q),
usr/src/uts/common/io/arn/arn_mac.c
852
REG_WRITE(ah, AR_DCHNTIME(q),
usr/src/uts/common/io/arn/arn_mac.c
858
REG_WRITE(ah, AR_QMISC(q),
usr/src/uts/common/io/arn/arn_mac.c
865
REG_WRITE(ah, AR_DMISC(q),
usr/src/uts/common/io/arn/arn_mac.c
870
REG_WRITE(ah, AR_DMISC(q),
usr/src/uts/common/io/arn/arn_mac.c
876
REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |
usr/src/uts/common/io/arn/arn_mac.c
881
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
usr/src/uts/common/io/arn/arn_mac.c
888
REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |
usr/src/uts/common/io/arn/arn_mac.c
896
REG_WRITE(ah, AR_QRDYTIMECFG(q),
usr/src/uts/common/io/arn/arn_mac.c
898
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
usr/src/uts/common/io/arn/arn_mac.c
903
REG_WRITE(ah, AR_QMISC(q),
usr/src/uts/common/io/arn/arn_mac.c
907
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
usr/src/uts/common/io/arn/arn_mac.c
915
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
usr/src/uts/common/io/arn/arn_phy.c
102
REG_WRITE(ah, AR_PHY(0x37), reg32);
usr/src/uts/common/io/arn/arn_phy.c
137
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
usr/src/uts/common/io/arn/arn_phy.c
140
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
usr/src/uts/common/io/arn/arn_phy.c
173
REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
usr/src/uts/common/io/arn/arn_phy.c
431
REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
usr/src/uts/common/io/arn/arn_phy.c
445
REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
usr/src/uts/common/io/arn/arn_phy.c
447
REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
usr/src/uts/common/io/arn/arn_phy.c
72
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
usr/src/uts/common/io/arn/arn_phy.c
75
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
usr/src/uts/common/io/arn/arn_phy.h
529
REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
usr/src/uts/common/io/qede/579xx/hsi/hw/misc_bits.h
256
REG_WRITE(path, _reg_ ## _CLEAR, _bits_); \
usr/src/uts/common/io/qede/579xx/hsi/hw/misc_bits.h
257
REG_WRITE(path, _reg_ ## _SET, _bits_); \