REG_READ - Illumos

usr/src/uts/common/io/arn/arn_ani.c

237

stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);

usr/src/uts/common/io/arn/arn_ani.c

238

stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);

usr/src/uts/common/io/arn/arn_ani.c

239

stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);

usr/src/uts/common/io/arn/arn_ani.c

240

stats->rts_good += REG_READ(ah, AR_RTS_OK);

usr/src/uts/common/io/arn/arn_ani.c

241

stats->beacons += REG_READ(ah, AR_BEACON_CNT);

usr/src/uts/common/io/arn/arn_ani.c

470

txFrameCount = REG_READ(ah, AR_TFCNT);

usr/src/uts/common/io/arn/arn_ani.c

471

rxFrameCount = REG_READ(ah, AR_RFCNT);

usr/src/uts/common/io/arn/arn_ani.c

472

cycleCount = REG_READ(ah, AR_CCCNT);

usr/src/uts/common/io/arn/arn_ani.c

601

phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);

usr/src/uts/common/io/arn/arn_ani.c

602

phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);

usr/src/uts/common/io/arn/arn_ani.c

715

uint32_t rc = REG_READ(ah, AR_RCCNT);

usr/src/uts/common/io/arn/arn_ani.c

716

uint32_t rf = REG_READ(ah, AR_RFCNT);

usr/src/uts/common/io/arn/arn_ani.c

717

uint32_t tf = REG_READ(ah, AR_TFCNT);

usr/src/uts/common/io/arn/arn_ani.c

718

uint32_t cc = REG_READ(ah, AR_CCCNT);

usr/src/uts/common/io/arn/arn_ani.c

763

if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))

usr/src/uts/common/io/arn/arn_ani.c

774

phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);

usr/src/uts/common/io/arn/arn_ani.c

775

phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);

usr/src/uts/common/io/arn/arn_ath9k.h

621

REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))

usr/src/uts/common/io/arn/arn_ath9k.h

624

(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))

usr/src/uts/common/io/arn/arn_ath9k.h

626

REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)

usr/src/uts/common/io/arn/arn_ath9k.h

628

REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)

usr/src/uts/common/io/arn/arn_calib.c

112

nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);

usr/src/uts/common/io/arn/arn_calib.c

114

nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);

usr/src/uts/common/io/arn/arn_calib.c

123

nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),

usr/src/uts/common/io/arn/arn_calib.c

126

nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),

usr/src/uts/common/io/arn/arn_calib.c

136

nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),

usr/src/uts/common/io/arn/arn_calib.c

146

nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),

usr/src/uts/common/io/arn/arn_calib.c

149

nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),

usr/src/uts/common/io/arn/arn_calib.c

159

nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),

usr/src/uts/common/io/arn/arn_calib.c

162

nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),

usr/src/uts/common/io/arn/arn_calib.c

172

nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),

usr/src/uts/common/io/arn/arn_calib.c

281

if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &

usr/src/uts/common/io/arn/arn_calib.c

340

REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

usr/src/uts/common/io/arn/arn_calib.c

342

REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

usr/src/uts/common/io/arn/arn_calib.c

344

(int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

usr/src/uts/common/io/arn/arn_calib.c

361

REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

usr/src/uts/common/io/arn/arn_calib.c

363

REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

usr/src/uts/common/io/arn/arn_calib.c

365

REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

usr/src/uts/common/io/arn/arn_calib.c

367

REG_READ(ah, AR_PHY_CAL_MEAS_3(i));

usr/src/uts/common/io/arn/arn_calib.c

387

(int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

usr/src/uts/common/io/arn/arn_calib.c

389

(int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

usr/src/uts/common/io/arn/arn_calib.c

391

(int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

usr/src/uts/common/io/arn/arn_calib.c

393

(int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_3(i));

usr/src/uts/common/io/arn/arn_calib.c

531

val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

usr/src/uts/common/io/arn/arn_calib.c

542

REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |

usr/src/uts/common/io/arn/arn_calib.c

591

val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

usr/src/uts/common/io/arn/arn_calib.c

601

REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |

usr/src/uts/common/io/arn/arn_calib.c

691

val = REG_READ(ah, ar5416_cca_regs[i]);

usr/src/uts/common/io/arn/arn_calib.c

705

if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &

usr/src/uts/common/io/arn/arn_calib.c

713

val = REG_READ(ah, ar5416_cca_regs[i]);

usr/src/uts/common/io/arn/arn_calib.c

729

if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {

usr/src/uts/common/io/arn/arn_calib.c

881

regList[i][1] = REG_READ(ah, regList[i][0]);

usr/src/uts/common/io/arn/arn_calib.c

883

regVal = REG_READ(ah, 0x7834);

usr/src/uts/common/io/arn/arn_calib.c

886

regVal = REG_READ(ah, 0x9808);

usr/src/uts/common/io/arn/arn_calib.c

902

ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);

usr/src/uts/common/io/arn/arn_calib.c

911

regVal = REG_READ(ah, 0x7834);

usr/src/uts/common/io/arn/arn_calib.c

915

regVal = REG_READ(ah, 0x7834);

usr/src/uts/common/io/arn/arn_calib.c

917

reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);

usr/src/uts/common/io/arn/arn_calib.c

924

reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);

usr/src/uts/common/io/arn/arn_calib.c

926

offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);

usr/src/uts/common/io/arn/arn_calib.c

927

offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);

usr/src/uts/common/io/arn/arn_calib.c

937

regVal = REG_READ(ah, 0x7834);

usr/src/uts/common/io/arn/arn_calib.c

940

regVal = REG_READ(ah, 0x9808);

usr/src/uts/common/io/arn/arn_calib.c

962

REG_READ(ah, AR_PHY_AGC_CONTROL) |

usr/src/uts/common/io/arn/arn_calib.c

976

REG_READ(ah, AR_PHY_AGC_CONTROL) |

usr/src/uts/common/io/arn/arn_eeprom.c

1054

(uint16_t)(MS(REG_READ(ah, AR_PHY_TPCRG5),

usr/src/uts/common/io/arn/arn_eeprom.c

1179

pdGainOverlap_t2 = (uint16_t)(MS(REG_READ(ah, AR_PHY_TPCRG5),

usr/src/uts/common/io/arn/arn_eeprom.c

133

(void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

usr/src/uts/common/io/arn/arn_eeprom.c

141

*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),

usr/src/uts/common/io/arn/arn_eeprom.c

2231

(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &

usr/src/uts/common/io/arn/arn_eeprom.c

2273

(REG_READ(ah,

usr/src/uts/common/io/arn/arn_eeprom.c

2283

(REG_READ(ah,

usr/src/uts/common/io/arn/arn_eeprom.c

2305

(REG_READ(ah,

usr/src/uts/common/io/arn/arn_eeprom.c

2314

(REG_READ(ah,

usr/src/uts/common/io/arn/arn_eeprom.c

2455

(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &

usr/src/uts/common/io/arn/arn_eeprom.c

2487

regVal = REG_READ(ah, 0x99ac);

usr/src/uts/common/io/arn/arn_eeprom.c

2495

regVal = REG_READ(ah, 0x99ac);

usr/src/uts/common/io/arn/arn_eeprom.c

2496

regVal = REG_READ(ah, 0xa208);

usr/src/uts/common/io/arn/arn_eeprom.c

2500

regVal = REG_READ(ah, 0xa208);

usr/src/uts/common/io/arn/arn_eeprom.c

66

regVal = REG_READ(ah, reg) & ~mask;

usr/src/uts/common/io/arn/arn_hw.c

1044

synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

usr/src/uts/common/io/arn/arn_hw.c

1179

REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);

usr/src/uts/common/io/arn/arn_hw.c

120

if ((REG_READ(ah, reg) & mask) == val)

usr/src/uts/common/io/arn/arn_hw.c

1204

REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);

usr/src/uts/common/io/arn/arn_hw.c

127

reg, REG_READ(ah, reg), mask, val));

usr/src/uts/common/io/arn/arn_hw.c

1280

REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);

usr/src/uts/common/io/arn/arn_hw.c

1587

regval = REG_READ(ah, AR_AHB_MODE);

usr/src/uts/common/io/arn/arn_hw.c

1590

regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;

usr/src/uts/common/io/arn/arn_hw.c

1595

regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;

usr/src/uts/common/io/arn/arn_hw.c

1614

val = REG_READ(ah, AR_STA_ID1);

usr/src/uts/common/io/arn/arn_hw.c

1703

tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);

usr/src/uts/common/io/arn/arn_hw.c

1791

enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &

usr/src/uts/common/io/arn/arn_hw.c

1916

synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

usr/src/uts/common/io/arn/arn_hw.c

2012

tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

usr/src/uts/common/io/arn/arn_hw.c

2236

tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

usr/src/uts/common/io/arn/arn_hw.c

2451

saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);

usr/src/uts/common/io/arn/arn_hw.c

2455

macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

usr/src/uts/common/io/arn/arn_hw.c

2457

saveLedState = REG_READ(ah, AR_CFG_LED) &

usr/src/uts/common/io/arn/arn_hw.c

2560

REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

usr/src/uts/common/io/arn/arn_hw.c

2589

mask = REG_READ(ah, AR_CFG);

usr/src/uts/common/io/arn/arn_hw.c

2600

__func__, REG_READ(ah, AR_CFG)));

usr/src/uts/common/io/arn/arn_hw.c

2631

keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));

usr/src/uts/common/io/arn/arn_hw.c

2826

uint32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));

usr/src/uts/common/io/arn/arn_hw.c

2874

if ((REG_READ(ah, AR_RTC_STATUS) &

usr/src/uts/common/io/arn/arn_hw.c

2890

val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;

usr/src/uts/common/io/arn/arn_hw.c

3029

host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);

usr/src/uts/common/io/arn/arn_hw.c

3033

host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);

usr/src/uts/common/io/arn/arn_hw.c

304

val = REG_READ(ah, AR_SREV) & AR_SREV_ID;

usr/src/uts/common/io/arn/arn_hw.c

3053

if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {

usr/src/uts/common/io/arn/arn_hw.c

3054

if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)

usr/src/uts/common/io/arn/arn_hw.c

3056

isr = REG_READ(ah, AR_ISR);

usr/src/uts/common/io/arn/arn_hw.c

3060

sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &

usr/src/uts/common/io/arn/arn_hw.c

3069

isr = REG_READ(ah, AR_ISR);

usr/src/uts/common/io/arn/arn_hw.c

307

val = REG_READ(ah, AR_SREV);

usr/src/uts/common/io/arn/arn_hw.c

3075

isr2 = REG_READ(ah, AR_ISR_S2);

usr/src/uts/common/io/arn/arn_hw.c

3090

isr = REG_READ(ah, AR_ISR_RAC);

usr/src/uts/common/io/arn/arn_hw.c

3112

s0_s = REG_READ(ah, AR_ISR_S0_S);

usr/src/uts/common/io/arn/arn_hw.c

3116

s1_s = REG_READ(ah, AR_ISR_S1_S);

usr/src/uts/common/io/arn/arn_hw.c

3128

uint32_t isr5 = REG_READ(ah, AR_ISR_S5_S);

usr/src/uts/common/io/arn/arn_hw.c

3173

(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);

usr/src/uts/common/io/arn/arn_hw.c

3203

(void) REG_READ(ah, AR_IER);

usr/src/uts/common/io/arn/arn_hw.c

3206

(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);

usr/src/uts/common/io/arn/arn_hw.c

3209

(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);

usr/src/uts/common/io/arn/arn_hw.c

3257

mask = REG_READ(ah, AR_IMR_S2) &

usr/src/uts/common/io/arn/arn_hw.c

332

val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;

usr/src/uts/common/io/arn/arn_hw.c

3657

return ((REG_READ(ah, AR_PHY_CCK_DETECT) &

usr/src/uts/common/io/arn/arn_hw.c

3667

if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {

usr/src/uts/common/io/arn/arn_hw.c

372

regHold[i] = REG_READ(ah, addr);

usr/src/uts/common/io/arn/arn_hw.c

3729

v = REG_READ(ah, AR_PHY_CCK_DETECT);

usr/src/uts/common/io/arn/arn_hw.c

376

rdData = REG_READ(ah, addr);

usr/src/uts/common/io/arn/arn_hw.c

3776

tmp = REG_READ(ah, addr);

usr/src/uts/common/io/arn/arn_hw.c

3806

return ((MS(REG_READ(ah, AR_GPIO_IN_OUT),

usr/src/uts/common/io/arn/arn_hw.c

3809

return ((MS(REG_READ(ah,

usr/src/uts/common/io/arn/arn_hw.c

3878

return (REG_READ(ah, AR_DEF_ANTENNA) & 0x7);

usr/src/uts/common/io/arn/arn_hw.c

390

rdData = REG_READ(ah, addr);

usr/src/uts/common/io/arn/arn_hw.c

3940

uint32_t bits = REG_READ(ah, AR_RX_FILTER);

usr/src/uts/common/io/arn/arn_hw.c

3941

uint32_t phybits = REG_READ(ah, AR_PHY_ERR);

usr/src/uts/common/io/arn/arn_hw.c

3967

REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);

usr/src/uts/common/io/arn/arn_hw.c

3970

REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);

usr/src/uts/common/io/arn/arn_hw.c

4078

tsf = REG_READ(ah, AR_TSF_U32);

usr/src/uts/common/io/arn/arn_hw.c

4079

tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);

usr/src/uts/common/io/arn/arn_hw.c

4090

while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {

usr/src/uts/common/io/arn/arn_hw.c

767

ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);

usr/src/uts/common/io/arn/arn_mac.c

1047

reg = REG_READ(ah, AR_OBS_BUS_1);

usr/src/uts/common/io/arn/arn_mac.c

1102

REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)));

usr/src/uts/common/io/arn/arn_mac.c

120

REG_READ(ah, AR_OBS_BUS_1)));

usr/src/uts/common/io/arn/arn_mac.c

122

"AR_CR 0x%x \n", REG_READ(ah, AR_CR)));

usr/src/uts/common/io/arn/arn_mac.c

128

return (REG_READ(ah, AR_QTXDP(q)));

usr/src/uts/common/io/arn/arn_mac.c

155

npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;

usr/src/uts/common/io/arn/arn_mac.c

158

if (REG_READ(ah, AR_Q_TXE) & (1 << q))

usr/src/uts/common/io/arn/arn_mac.c

178

txcfg = REG_READ(ah, AR_TXCFG);

usr/src/uts/common/io/arn/arn_mac.c

216

tsfLow = REG_READ(ah, AR_TSF_L32);

usr/src/uts/common/io/arn/arn_mac.c

222

if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))

usr/src/uts/common/io/arn/arn_mac.c

71

val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof (uint32_t)));

usr/src/uts/common/io/arn/arn_mac.c

842

REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |

usr/src/uts/common/io/arn/arn_mac.c

859

REG_READ(ah, AR_QMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

866

REG_READ(ah, AR_DMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

871

REG_READ(ah, AR_DMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

876

REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

881

REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

888

REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

898

REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

904

REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);

usr/src/uts/common/io/arn/arn_mac.c

907

REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |

usr/src/uts/common/io/arn/arn_mac.c

915

REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |

usr/src/uts/common/io/arn/arn_phy.c

123

reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);

usr/src/uts/common/io/arn/arn_phy.c

134

txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);

usr/src/uts/common/io/arn/arn_phy.c

448

(REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)

usr/src/uts/common/io/arn/arn_phy.c

449

| ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));

usr/src/uts/common/io/arn/arn_phy.c

69

txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);