REG_RD32
if ((REG_RD32(qlt, REG_RISC_STATUS) & BIT_8) == 0) {
(REG_RD32(qlt, REG_RISC_STATUS) & BIT_8) == 0;
if (!(REG_RD32(qlt, REG_CTRL_STATUS) & DMA_ACTIVE_STATUS)) {
if (!(REG_RD32(qlt, REG_CTRL_STATUS) & CHIP_SOFT_RESET)) {
stat = REG_RD32(qlt, REG_RISC_STATUS);
instance, (long long)ret, REG_RD32(qlt, REG_INTR_STATUS));
val1 = REG_RD32(qlt, REG_REQ_OUT_PTR);
val2 = REG_RD32(qlt, REG_REQ_OUT_PTR);
val3 = REG_RD32(qlt, REG_REQ_OUT_PTR);
val1 = REG_RD32(qlt, REG_PREQ_OUT_PTR);
val2 = REG_RD32(qlt, REG_PREQ_OUT_PTR);
val3 = REG_RD32(qlt, REG_PREQ_OUT_PTR);
(void) REG_RD32(qlt, REG_INTR_CTRL);
while (REG_RD32(qlt, REG_CTRL_STATUS) & DMA_ACTIVE_STATUS) {
while ((REG_RD32(qlt, REG_INTR_STATUS) & RISC_PCI_INTR_REQUEST) == 0) {
status = (REG_RD32(qlt, REG_RISC_STATUS) & FW_INTR_STATUS_MASK);
risc_status = REG_RD32(qlt, REG_RISC_STATUS);
(uint16_t)REG_RD32(qlt, REG_ATIO_IN_PTR);
risc_status = REG_RD32(qlt, REG_RISC_STATUS);
hccsr = REG_RD32(qlt, REG_HCCR);
(uint16_t)REG_RD32(qlt, REG_ATIO_IN_PTR);
(uint16_t)REG_RD32(qlt, REG_ATIO_IN_PTR);
REG_RD32(qlt, REG_ATIO_IN_PTR);
risc_status = REG_RD32(qlt, REG_RISC_STATUS);
(uint16_t)REG_RD32(qlt, REG_ATIO_IN_PTR);
(uint16_t)REG_RD32(qlt, REG_RESP_IN_PTR);
(uint16_t)REG_RD32(qlt, REG_ATIO_IN_PTR);
REG_RD32(qlt, REG_ATIO_IN_PTR);
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting */
risc_status = REG_RD32(qlt, REG_RISC_STATUS);
REG_RD32(qlt, REG_CTRL_STATUS) | FLASH_ERROR);
if (REG_RD32(qlt, REG_FLASH_ADDR) & BIT_31) {
} else if (REG_RD32(qlt, REG_CTRL_STATUS) & FLASH_ERROR) {
*bp = REG_RD32(qlt, REG_FLASH_DATA);
func = ((REG_RD32(qlt, REG_CTRL_STATUS) & 0x0000f000) >> 12);
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & FUNCTION_NUMBER ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & FUNCTION_NUMBER ?
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */
func = ((REG_RD32(qlt, REG_CTRL_STATUS) & 0x0000f000) >> 12);
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & BIT_12 ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & FUNCTION_NUMBER ?
addr = REG_RD32(qlt, REG_CTRL_STATUS) & FUNCTION_NUMBER ?
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */
(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */
uint32_t pci_bits = REG_RD32(qlt, REG_CTRL_STATUS);
qlt->fw_subminor, qlt->fw_attr, REG_RD32(qlt, REG_RISC_STATUS));
if (REG_RD32(qlt, REG_RISC_STATUS) & 0x100) {
n = (int)snprintf(buf, size_left, "%08x ", REG_RD32(qlt, 0xFC));
"\n\nRISC IO register\n%08x", REG_RD32(qlt, 0xC0));
"%08x%c", REG_RD32(qlt, startaddr + (i << 2)), c));