usr/src/uts/common/io/comstar/port/qlt/qlt.c

10284

REG_WR32(qlt, REG_HCCR, 0x30000000);

usr/src/uts/common/io/comstar/port/qlt/qlt.c

1040

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_HOST_TO_RISC_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

1050

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_HOST_TO_RISC_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

1055

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

1059

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

2041

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

2053

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

2086

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3469

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3492

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3514

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3577

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3606

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_HOST_TO_RISC_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3656

REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3753

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_HOST_TO_RISC_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3824

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3842

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3858

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3918

hccsr = REG_RD32(qlt, REG_HCCR);

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3939

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3943

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3949

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3963

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3967

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

3990

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4005

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4163

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4172

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4267

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4270

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4278

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4292

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4296

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4299

REG_WR32(qlt, REG_HCCR,

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4322

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4333

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4487

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4496

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4499

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4592

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4593

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4611

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4612

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4677

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4678

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4696

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4697

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4831

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4832

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4850

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

4851

(void) REG_RD32(qlt, REG_HCCR); /* PCI Posting. */

usr/src/uts/common/io/comstar/port/qlt/qlt.c

7802

REG_WR32(qlt, REG_HCCR, HCCR_CMD(SET_RISC_PAUSE));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

9080

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

9117

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

9716

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

9748

REG_WR32(qlt, REG_HCCR, HCCR_CMD(CLEAR_RISC_TO_PCI_INTR));