usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c

137

{ "gsbase", REG_GSBASE, MDB_TGT_R_EXPORT },

usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c

277

mdb_printf("%%gsbase = 0x%0?p\n", grs[REG_GSBASE]);

usr/src/cmd/mdb/intel/modules/genunix/gcore_isadep.c

74

grp[REG_GSBASE] = pcb->pcb_gsbase;

usr/src/lib/libproc/common/Pcore.c

582

lwp->lwp_status.pr_reg[REG_GSBASE] = prs64->pr_reg.lxr_gs_base;

usr/src/uts/intel/dtrace/fasttrap_isa.c

1664

case REG_GSBASE: return (rdmsr(MSR_AMD_GSBASE));

usr/src/uts/intel/fs/proc/prmachdep.c

128

dst[REG_GSBASE] = lwp->lwp_pcb.pcb_gsbase;

usr/src/uts/intel/os/archdep.c

309

grp[REG_GSBASE] = pcb->pcb_gsbase;

usr/src/uts/intel/os/archdep.c

587

pcb->pcb_gsbase = grp[REG_GSBASE];

usr/src/uts/intel/os/sundep.c

357

(uintptr_t)grp[REG_GSBASE]);