usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c

136

{ "fsbase", REG_FSBASE, MDB_TGT_R_EXPORT },

usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c

278

mdb_printf("%%fsbase = 0x%0?p\n", grs[REG_FSBASE]);

usr/src/cmd/mdb/intel/modules/genunix/gcore_isadep.c

73

grp[REG_FSBASE] = pcb->pcb_fsbase;

usr/src/lib/libc/amd64/threads/machdep.c

77

ucp->uc_mcontext.gregs[REG_FSBASE] = (greg_t)ulwp;

usr/src/lib/libc/port/threads/sigaction.c

576

uc.uc_mcontext.gregs[REG_FSBASE] = (greg_t)self;

usr/src/lib/libproc/common/Pcore.c

583

lwp->lwp_status.pr_reg[REG_FSBASE] = prs64->pr_reg.lxr_fs_base;

usr/src/uts/intel/dtrace/fasttrap_isa.c

1663

case REG_FSBASE: return (rdmsr(MSR_AMD_FSBASE));

usr/src/uts/intel/fs/proc/prmachdep.c

129

dst[REG_FSBASE] = lwp->lwp_pcb.pcb_fsbase;

usr/src/uts/intel/os/archdep.c

308

grp[REG_FSBASE] = pcb->pcb_fsbase;

usr/src/uts/intel/os/archdep.c

586

pcb->pcb_fsbase = grp[REG_FSBASE];

usr/src/uts/intel/os/sundep.c

353

(uintptr_t)grp[REG_FSBASE]);