REG_CLR_BIT
REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET),
REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
REG_CLR_BIT(ah, AR_DIAG_SW,
REG_CLR_BIT(ah, AR_DIAG_SW,
REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);