usr/src/uts/common/io/arn/arn_ani.c

134

REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,

usr/src/uts/common/io/arn/arn_calib.c

698

REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

usr/src/uts/common/io/arn/arn_calib.c

700

REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

usr/src/uts/common/io/arn/arn_hw.c

1620

REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);

usr/src/uts/common/io/arn/arn_hw.c

2002

REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,

usr/src/uts/common/io/arn/arn_hw.c

2006

REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,

usr/src/uts/common/io/arn/arn_hw.c

2840

REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,

usr/src/uts/common/io/arn/arn_hw.c

2845

REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET),

usr/src/uts/common/io/arn/arn_hw.c

2861

REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,

usr/src/uts/common/io/arn/arn_hw.c

2907

REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

usr/src/uts/common/io/arn/arn_hw.c

3273

REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);

usr/src/uts/common/io/arn/arn_hw.c

3845

REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,

usr/src/uts/common/io/arn/arn_mac.c

1044

REG_CLR_BIT(ah, AR_DIAG_SW,

usr/src/uts/common/io/arn/arn_mac.c

1056

REG_CLR_BIT(ah, AR_DIAG_SW,

usr/src/uts/common/io/arn/arn_mac.c

1082

REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

usr/src/uts/common/io/arn/arn_mac.c

233

REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);

usr/src/uts/common/io/arn/arn_mac.c

248

REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);