REG
fraglen = interpret_extensions(regext_data, regext_size, REG);
REG(expr0->data.itm_exnum) : \
c = REG(expr->data.itm_exnum);
#define EVAL_EXPR_R(n) (REG((itm_num_t)(expr->data.operand[(n)].itm_ptr)))
REG(expr0->data.itm_exnum) : \
return (REG(expr->data.itm_exnum));
send((SrvLocMsg)rec[REG]);
private final static int REG = 1;
#define VR0_(REG, ...) "ymm"#REG
#define VR1_(_1, REG, ...) "ymm"#REG
#define VR2_(_1, _2, REG, ...) "ymm"#REG
#define VR3_(_1, _2, _3, REG, ...) "ymm"#REG
#define VR4_(_1, _2, _3, _4, REG, ...) "ymm"#REG
#define VR5_(_1, _2, _3, _4, _5, REG, ...) "ymm"#REG
#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "ymm"#REG
#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "ymm"#REG
#define R_23(REG...) _R_23(REG, 1, 2, 3)
#define VR0_(REG, ...) "xmm"#REG
#define VR1_(_1, REG, ...) "xmm"#REG
#define VR2_(_1, _2, REG, ...) "xmm"#REG
#define VR3_(_1, _2, _3, REG, ...) "xmm"#REG
#define VR4_(_1, _2, _3, _4, REG, ...) "xmm"#REG
#define VR5_(_1, _2, _3, _4, _5, REG, ...) "xmm"#REG
#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "xmm"#REG
#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "xmm"#REG
#define VR0_(REG, ...) "xmm"#REG
#define VR1_(_1, REG, ...) "xmm"#REG
#define VR2_(_1, _2, REG, ...) "xmm"#REG
#define VR3_(_1, _2, _3, REG, ...) "xmm"#REG
#define VR4_(_1, _2, _3, _4, REG, ...) "xmm"#REG
#define VR5_(_1, _2, _3, _4, _5, REG, ...) "xmm"#REG
#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "xmm"#REG
#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "xmm"#REG
#define R_23(REG...) _R_23(REG, 1, 2, 3)
(uint8_t *)(REG)+\
#define EPIC_WRITE(HANDLE, REG, ADDR, MASK, DATA)\
(uint8_t *)(REG)+\
(uint8_t *)(REG)+\
(uint8_t *)(REG)+\
#define EPIC_RD(HANDLE, REG, LHS)\
(uint8_t *)(REG)+\
#define EPIC_WR(HANDLE, REG, DATA)\
(uint8_t *)(REG)+\
#define EPIC_READ(HANDLE, REG, LHS, ADDR)\
(uint8_t *)(REG)+\
#define MMU_FAULT_STATUS_AREA(REG) \
ldxa [%g0]ASI_SCRATCHPAD, REG