RD32_IO_REG
RD32_IO_REG(ha, ctrl_status) | FLASH_NVRAM_ACCESS_ERROR);
if (RD32_IO_REG(ha, flash_address) & FLASH_DATA_FLAG) {
} else if (RD32_IO_REG(ha, ctrl_status) & FLASH_NVRAM_ACCESS_ERROR) {
*bp = RD32_IO_REG(ha, flash_data);
RD32_IO_REG(ha, ctrl_status) | FLASH_NVRAM_ACCESS_ERROR);
RD32_IO_REG(ha, flash_data); /* PCI Posting. */
if ((RD32_IO_REG(ha, flash_address) & FLASH_DATA_FLAG) == 0) {
} else if (RD32_IO_REG(ha, ctrl_status) & FLASH_NVRAM_ACCESS_ERROR) {
RD32_IO_REG(ha, ctrl_status) | ISP_FLASH_ENABLE);
RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */
RD32_IO_REG(ha, ctrl_status) | ISP_FLASH_ENABLE);
RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */
RD32_IO_REG(ha, ctrl_status) & ~ISP_FLASH_ENABLE);
RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */
fw->hccr = RD32_IO_REG(ha, hccr);
if ((RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0) {
(RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0 &&
RD32_IO_REG(ha, io_base_addr);
fw->hccr = RD32_IO_REG(ha, hccr);
fw->r2h_status = RD32_IO_REG(ha, risc2host);
if ((RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0) {
(RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0 &&
RD32_IO_REG(ha, io_base_addr);
fw->hccr = RD32_IO_REG(ha, hccr);
fw->r2h_status = RD32_IO_REG(ha, risc2host);
if ((RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0) {
(RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0 &&
RD32_IO_REG(ha, io_base_addr);
RD32_IO_REG(ha, hccr);
RD32_IO_REG(ha, hccr);
fw->hccr = RD32_IO_REG(ha, hccr);
fw->r2h_status = RD32_IO_REG(ha, risc2host);
if ((RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0) {
(RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0 &&
RD32_IO_REG(ha, io_base_addr);
if ((RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0) {
(RD32_IO_REG(ha, risc2host) & RH_RISC_PAUSED) == 0;
if (!(RD32_IO_REG(ha, ctrl_status) & DMA_ACTIVE)) {
if (!(RD32_IO_REG(ha, ctrl_status) & ISP_RESET)) {
stat = RD32_IO_REG(ha, risc2host);
stat = RD32_IO_REG(ha, risc2host);
stat = RD32_IO_REG(ha, risc2host);
stat = RD32_IO_REG(ha, risc2host);
if ((RD32_IO_REG(ha, ctrl_status) & DMA_ACTIVE) == 0) {
stat = RD32_IO_REG(ha, risc2host);
if ((RD32_IO_REG(ha, ctrl_status) & ISP_RESET) == 0) {
stat = RD32_IO_REG(ha, risc2host);
RD32_IO_REG(ha, ctrl_status) | ISP_FLASH_ENABLE);
RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */
RD32_IO_REG(ha, ctrl_status) & ~ISP_FLASH_ENABLE);
RD32_IO_REG(ha, ctrl_status); /* PCI Posting. */
(void) RD32_IO_REG(ha, ictrl); /* PCI posting */
(void) RD32_IO_REG(ha, ictrl); /* PCI posting */
RD32_IO_REG(ha, hccr); /* PCI posting. */
if (((stat = RD32_IO_REG(ha, risc2host)) & RH_RISC_INT) == 0) {
RD32_IO_REG(ha, nx_risc_int) == 0) {
(~(RD32_IO_REG(ha, gpiod)));
gpio_data = RD32_IO_REG(ha, gpiod);
gpio_data = RD32_IO_REG(ha, gpiod);
gpio_data = RD32_IO_REG(ha, gpiod);
RD32_IO_REG(ha, nx_risc_int) & NX_RISC_INT : \