RD16_IO_REG
data = (uint16_t)(RD16_IO_REG(ha, ctrl_status) |
data = (uint16_t)(RD16_IO_REG(ha, ctrl_status) &
bank_select = (uint16_t)RD16_IO_REG(ha, ctrl_status);
bank_select = RD16_IO_REG(ha, ctrl_status);
data = (uint8_t)RD16_IO_REG(ha, flash_data);
while ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == 0) {
while (RD16_IO_REG(ha, mailbox_out[0]) == MBS_ROM_BUSY) {
while ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == 0) {
if (RD16_IO_REG(ha, semaphore) &
mcp->mb[0] = RD16_IO_REG(ha,
RD16_IO_REG(ha,
while ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == 0) {
while (RD16_IO_REG(ha, mailbox_out[0]) == MBS_ROM_BUSY) {
(RD16_IO_REG(ha, risc2host) & 0xff);
RD16_IO_REG(ha,
RD16_IO_REG(ha,
RD16_IO_REG(ha,
rval = RD16_IO_REG(ha, mailbox_out[0]);
RD16_IO_REG(ha, hccr);
RD16_IO_REG(ha, hccr);
ha->rom_status = RD16_IO_REG(ha, mailbox_out[0]);
rval = RD16_IO_REG(ha, mailbox_out[0]);
RD16_IO_REG(ha, hccr),
RD16_IO_REG(ha, istatus));
if ((RD16_IO_REG(ha, nvram) & 0x8000) == 0) {
if (RD16_IO_REG(ha, host_to_host_sema) & 1) {
if ((RD16_IO_REG(ha, host_to_host_sema) & 1) == 0) {
if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) !=
if (RD16_IO_REG(ha, fb_cmd) == 6) {
if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) ==
if ((RD16_IO_REG(ha, ctrl_status) & ISP_FUNC_NUM_MASK)
if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != 0) {
if ((RD16_IO_REG(ha, fb_cmd) & 0xff) == 0) {
if ((RD16_IO_REG(ha, ctrl_status) & ISP_RESET) == 0) {
if (RD16_IO_REG(ha, mailbox_out[0]) != MBS_ROM_BUSY) {
RD16_IO_REG(ha, mailbox_out[7]) == 4) {
if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != 0) {
ha->rom_status = RD16_IO_REG(ha, mailbox_out[0]);
ha->adapter_stats->revlvl.isp2200 = RD16_IO_REG(ha, mailbox_out[4]);
ha->adapter_stats->revlvl.risc = RD16_IO_REG(ha, mailbox_out[5]);
ha->adapter_stats->revlvl.frmbfr = RD16_IO_REG(ha, mailbox_out[6]);
ha->adapter_stats->revlvl.riscrom = RD16_IO_REG(ha, mailbox_out[8]);
reg_data = RD16_IO_REG(ha, nvram);
cnt = RD16_IO_REG(ha, req_out);
index = RD16_IO_REG(ha, mailbox_out[8]);
index1 = RD16_IO_REG(ha, mailbox_out[8]);
cnt = RD16_IO_REG(ha, req_out);
data = RD16_IO_REG(ha, nvram);
word = RD16_IO_REG(ha, nvram);
word = RD16_IO_REG(ha, nvram);
"\n", mb[0], RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]));
ha->iidma_rate = RD16_IO_REG(ha, mailbox_out[1]);
"mbx4=%xh\n", mb[0], RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]),
RD16_IO_REG(ha, mailbox_out[3]),
RD16_IO_REG(ha, mailbox_out[4]));
ha->sfp_stat = RD16_IO_REG(ha, mailbox_out[2]);
mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
RD16_IO_REG(ha, mailbox_out[3]) : 0);
(void) RD16_IO_REG(ha, ictrl); /* PCI posting */
mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
RD16_IO_REG(ha, mailbox_out[3]) : 0);
RD16_IO_REG(ha, mailbox_out[1]));
mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
mb[3] = RD16_IO_REG(ha, mailbox_out[3]);
mb[index] = RD16_IO_REG(ha, mailbox_out[index]);
"mbx1=%xh\n", mb[0], RD16_IO_REG(ha, mailbox_out[1]));
mb[0], RD16_IO_REG(ha, mailbox_out[1]));
mb[0], RD16_IO_REG(ha, mailbox_out[1]));
mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
rsp_q->isp_rsp_index = RD16_IO_REG(ha, resp_in);
mb[0], RD16_IO_REG(ha, mailbox_out[1]));
mb[0], RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]));
RD16_IO_REG(ha, mailbox_out[1]));
mb[0], RD16_IO_REG(ha, mailbox_out[1]));
mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
ha->idc_mb[cnt] = RD16_IO_REG(ha, mailbox_out[cnt]);
mb[0], RD16_IO_REG(ha, mailbox_out[2]));
"mbx3=%xh\n", mb[0], RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]),
RD16_IO_REG(ha, mailbox_out[3]));
(void) RD16_IO_REG(ha, ictrl); /* PCI posting */
RD16_IO_REG(ha, hccr); /* PCI posting. */
if (RD16_IO_REG(ha, istatus) & RISC_INT) {
stat = RD16_IO_REG(ha, semaphore);
mbx = RD16_IO_REG(ha, mailbox_out[0]);
rsp_q->isp_rsp_index = RD16_IO_REG(ha, resp_in);
hccr_reg = RD16_IO_REG(ha, hccr);
ha->mcp->mb[cnt] = RD16_IO_REG(ha,
handles[0] = SHORT_TO_LONG(RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]));
handles[0] = (uint32_t)RD16_IO_REG(ha, mailbox_out[1]);
handles[1] = (uint32_t)RD16_IO_REG(ha, mailbox_out[2]);
handles[0] = (uint32_t)RD16_IO_REG(ha, mailbox_out[1]);
handles[1] = (uint32_t)RD16_IO_REG(ha, mailbox_out[2]);
handles[2] = (uint32_t)RD16_IO_REG(ha, mailbox_out[3]);
handles[0] = (uint32_t)RD16_IO_REG(ha, mailbox_out[1]);
handles[1] = (uint32_t)RD16_IO_REG(ha, mailbox_out[2]);
handles[2] = (uint32_t)RD16_IO_REG(ha, mailbox_out[3]);
handles[3] = (uint32_t)RD16_IO_REG(ha, mailbox_out[6]);
handles[0] = (uint32_t)RD16_IO_REG(ha, mailbox_out[1]);
handles[1] = (uint32_t)RD16_IO_REG(ha, mailbox_out[2]);
handles[2] = (uint32_t)RD16_IO_REG(ha, mailbox_out[3]);
handles[3] = (uint32_t)RD16_IO_REG(ha, mailbox_out[6]);
handles[4] = (uint32_t)RD16_IO_REG(ha, mailbox_out[7]);
RD16_IO_REG(ha, mailbox_out[2]));
RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]));
RD16_IO_REG(ha, mailbox_out[6]),
RD16_IO_REG(ha, mailbox_out[7]));
RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2])) :
SHORT_TO_LONG(MSW(mbx), RD16_IO_REG(ha, mailbox_out[2]));
RD16_IO_REG(ha, mailbox_out[1]),
RD16_IO_REG(ha, mailbox_out[2]),
RD16_IO_REG(ha, mailbox_out[3]),
RD16_IO_REG(ha, mailbox_out[6]),
RD16_IO_REG(ha, mailbox_out[7]));
mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
mb[3] = RD16_IO_REG(ha, mailbox_out[3]);
mb[7] = RD16_IO_REG(ha, mailbox_out[7]);
RD16_IO_REG(ha, mailbox_out[4]),
RD16_IO_REG(ha, mailbox_out[5]),
RD16_IO_REG(ha, mailbox_out[6]), mb[7],
RD16_IO_REG(ha, mailbox_out[8]),
RD16_IO_REG(ha, mailbox_out[9]),
RD16_IO_REG(ha, mailbox_out[10]),
RD16_IO_REG(ha, mailbox_out[11]),
RD16_IO_REG(ha, mailbox_out[12]));
mb[0], RD16_IO_REG(ha, mailbox_out[13]),
RD16_IO_REG(ha, mailbox_out[14]),
RD16_IO_REG(ha, mailbox_out[15]),
RD16_IO_REG(ha, mailbox_out[16]),
RD16_IO_REG(ha, mailbox_out[17]),
RD16_IO_REG(ha, mailbox_out[18]),
RD16_IO_REG(ha, mailbox_out[19]),
RD16_IO_REG(ha, mailbox_out[20]),
RD16_IO_REG(ha, mailbox_out[21]),
RD16_IO_REG(ha, mailbox_out[22]),
RD16_IO_REG(ha, mailbox_out[23]));
RD16_IO_REG(ha, mailbox_out[24]),
RD16_IO_REG(ha, mailbox_out[25]),
RD16_IO_REG(ha, mailbox_out[26]),
RD16_IO_REG(ha, mailbox_out[27]),
RD16_IO_REG(ha, mailbox_out[28]),
RD16_IO_REG(ha, mailbox_out[29]),
RD16_IO_REG(ha, mailbox_out[30]),
RD16_IO_REG(ha, mailbox_out[31]));
ha->errlog[3] = RD16_IO_REG(ha, mailbox_out[3]);
ha->errlog[2] = RD16_IO_REG(ha, mailbox_out[2]);
ha->errlog[1] = RD16_IO_REG(ha, mailbox_out[1]);
ha->errlog[3] = RD16_IO_REG(ha, mailbox_out[3]);
ha->errlog[2] = RD16_IO_REG(ha, mailbox_out[2]);
ha->errlog[1] = RD16_IO_REG(ha, mailbox_out[1]);
RD16_IO_REG(ha, mailbox_out[1]));
mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
mb[3] = RD16_IO_REG(ha, mailbox_out[3]);
(~(RD16_IO_REG(ha, gpiod)));
gpio_enable = (uint16_t)RD16_IO_REG(ha, gpioe);
gpio_data = (uint16_t)RD16_IO_REG(ha, gpiod);
RD16_IO_REG(ha, istatus) & RISC_INT)