RB_ADDR
CSR_WRITE_1(dev, RB_ADDR(port->p_txsq, RB_CTRL), RB_RST_SET);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_CLR);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_UTPP), utpp);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_LTPP), ltpp);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_ENA_OP_MD);
(void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL));
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_CLR);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_START), dev->d_txqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_END), dev->d_txqend[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_WP), dev->d_txqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_RP), dev->d_txqstart[pnum] / 8);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_STFWD);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_OP_MD);
(void) CSR_READ_1(dev, RB_ADDR(txq, RB_CTRL));
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
if (CSR_READ_1(dev, RB_ADDR(rxq, Q_RSL)) ==
CSR_READ_1(dev, RB_ADDR(rxq, Q_RL)))
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);