Q_WM
CSR_WRITE_2(dev, Q_ADDR(txq, Q_WM), MSK_BMU_TX_WM);
CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80);
CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM);