usr/src/uts/sun4/io/px/px.c

660

PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) {

usr/src/uts/sun4/io/px/px_ib.c

1017

PX_INTR_STATE_ENABLE, msiq_rec_type, msi_num)) != DDI_SUCCESS) {

usr/src/uts/sun4/io/px/px_intr.c

520

hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0);

usr/src/uts/sun4/io/px/px_intr.c

679

PX_INTR_STATE_ENABLE, msiq_rec_type, msi_num);

usr/src/uts/sun4/io/px/px_intr.c

871

if (ih_p->ih_intr_state == PX_INTR_STATE_ENABLE) {

usr/src/uts/sun4/io/px/px_pec.c

176

PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

200

PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

223

PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) {