usr/src/uts/sun4/io/px/px.c

705

PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG);

usr/src/uts/sun4/io/px/px_ib.c

791

ih_p->ih_intr_state = PX_INTR_STATE_DISABLE;

usr/src/uts/sun4/io/px/px_intr.c

165

if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) {

usr/src/uts/sun4/io/px/px_intr.c

524

hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_DISABLE, 0, 0);

usr/src/uts/sun4/io/px/px_intr.c

696

hdlp->ih_pri, PX_INTR_STATE_DISABLE, msiq_rec_type,

usr/src/uts/sun4/io/px/px_pec.c

264

PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

281

PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

297

PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG);