usr/src/uts/sun4/io/px/px_pec.c

184

hdl.ih_pri = PX_ERR_PIL;

usr/src/uts/sun4/io/px/px_pec.c

200

PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

208

hdl.ih_pri = PX_ERR_PIL;

usr/src/uts/sun4/io/px/px_pec.c

222

px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL,

usr/src/uts/sun4/io/px/px_pec.c

275

hdl.ih_pri = PX_ERR_PIL;

usr/src/uts/sun4/io/px/px_pec.c

281

PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

291

hdl.ih_pri = PX_ERR_PIL;

usr/src/uts/sun4/io/px/px_pec.c

297

PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG);

usr/src/uts/sun4u/io/px/px_lib4u.c

2101

VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL,

usr/src/uts/sun4u/io/px/px_lib4u.c

2119

VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0);

usr/src/uts/sun4u/io/px/px_lib4u.c

2205

VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL,

usr/src/uts/sun4u/io/px/px_lib4u.c

2297

VERIFY(rem_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL) == 0);

usr/src/uts/sun4v/io/px/px_lib4v.c

1947

VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL,

usr/src/uts/sun4v/io/px/px_lib4v.c

1968

VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0);

usr/src/uts/sun4v/io/px/px_lib4v.c

1987

VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL,