PX_ERR_PIL
hdl.ih_pri = PX_ERR_PIL;
PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC,
hdl.ih_pri = PX_ERR_PIL;
px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL,
hdl.ih_pri = PX_ERR_PIL;
PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC,
hdl.ih_pri = PX_ERR_PIL;
PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG);
VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL,
VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0);
VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL,
VERIFY(rem_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL) == 0);
VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL,
VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0);
VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL,