PUT_MIFREG
PUT_MIFREG(mif_imask, HME_MIF_INTMASK); /* mask all interrupts */
PUT_MIFREG(mif_cfg, GET_MIFREG(mif_cfg) | HME_MIF_CFGBB);
PUT_MIFREG(mif_cfg, GET_MIFREG(mif_cfg) & ~HME_MIF_CFGBB);
PUT_MIFREG(mif_bbdata, x);
PUT_MIFREG(mif_bbclk, HME_BBCLK_LOW);
PUT_MIFREG(mif_bbclk, HME_BBCLK_HIGH);
PUT_MIFREG(mif_bbclk, HME_BBCLK_LOW);
PUT_MIFREG(mif_bbclk, HME_BBCLK_HIGH);
PUT_MIFREG(mif_bbopenb, 1); /* Enable the MII driver */
PUT_MIFREG(mif_bbopenb, 0); /* Disable the MII driver */
PUT_MIFREG(mif_bbopenb, 1); /* Enable the MII driver */
PUT_MIFREG(mif_bbopenb, 0); /* Disable the MII driver */
PUT_MIFREG(mif_cfg, tmp_mif | HME_MIF_CFGPS);
PUT_MIFREG(mif_cfg, tmp_mif & ~(HME_MIF_CFGPS));
PUT_MIFREG(mif_cfg, tmp_mif);
PUT_MIFREG(mif_frame,
PUT_MIFREG(mif_cfg, tmp_mif);
PUT_MIFREG(mif_cfg, tmp_mif | HME_MIF_CFGPS);
PUT_MIFREG(mif_cfg, tmp_mif & ~(HME_MIF_CFGPS));
PUT_MIFREG(mif_cfg, tmp_mif);
PUT_MIFREG(mif_frame,
PUT_MIFREG(mif_cfg, tmp_mif);
PUT_MIFREG(mif_bbdata, x);
PUT_MIFREG(mif_bbclk, ERI_BBCLK_LOW);
PUT_MIFREG(mif_bbclk, ERI_BBCLK_HIGH);
PUT_MIFREG(mif_bbclk, ERI_BBCLK_LOW);
PUT_MIFREG(mif_bbclk, ERI_BBCLK_HIGH);
PUT_MIFREG(mif_bbopenb, 1); /* Enable the MII driver */
PUT_MIFREG(mif_bbopenb, 0); /* Disable the MII driver */
PUT_MIFREG(mif_bbopenb, 1); /* Enable the MII driver */
PUT_MIFREG(mif_bbopenb, 0); /* Disable the MII driver */
PUT_MIFREG(mif_frame, ERI_MIF_FRREAD |
PUT_MIFREG(mif_frame, (ERI_MIF_FRWRITE |
PUT_MIFREG(mif_cfg, erip->mif_config);
PUT_MIFREG(mif_cfg, erip->mif_config);
PUT_MIFREG(mif_cfg, erip->mif_config);
PUT_MIFREG(mif_imask, erip->mif_mask);
PUT_MIFREG(mif_cfg, erip->mif_config);
PUT_MIFREG(mif_imask, ERI_MIF_INTMASK);
PUT_MIFREG(mif_frame, \