PUT8
PUT8(M1575_PCMICR_REG, 0);
PUT8(M1575_PCMOCR_REG, 0);
PUT8(M1575_MICICR_REG, 0);
PUT8(M1575_CSPOCR_REG, 0);
PUT8(M1575_PCMI2CR_RR, 0);
PUT8(M1575_MICI2CR_RR, 0);
PUT8(M1575_PCMICR_REG, M1575_PCMICR_RR);
PUT8(M1575_PCMOCR_REG, M1575_PCMOCR_RR);
PUT8(M1575_MICICR_REG, M1575_MICICR_RR);
PUT8(M1575_CSPOCR_REG, M1575_CSPOCR_RR);
PUT8(M1575_PCMI2CR_REG, M1575_PCMI2CR_RR);
PUT8(M1575_MICI2CR_REG, M1575_MICI2CR_RR);
PUT8(M1575_PCMICR_REG, 0);
PUT8(M1575_PCMICR_REG, M1575_CR_RR);
PUT8(M1575_PCMILVIV_REG, M1575_BD_NUMS - 1);
PUT8(M1575_PCMICR_REG, 0);
PUT8(M1575_PCMOCR_REG, 0);
PUT8(M1575_PCMOCR_REG, M1575_CR_RR);
PUT8(M1575_PCMOLVIV_REG, M1575_BD_NUMS - 1);
PUT8(M1575_PCMOCR_REG, 0);
PUT8(lvioff, (civ - 1) % M1575_BD_NUMS);
#define SET8(reg, bit) PUT8(reg, GET8(reg) | (bit))
#define CLR8(reg, bit) PUT8(reg, GET8(reg) & ~(bit))
PUT8(dev, REG_IDXADDR, idx);
PUT8(dev, REG_IDXDATA, val);
PUT8(dev, REG_IDXADDR, idx);
PUT8(dev, REG_MIX3, v);
PUT8(dev, REG_VAUX, (((left * 15) / 100) << 4) | ((right * 15) / 100));
#define CLR8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) & ~(v))
#define SET8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) | (v))
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
#define CLR8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) & ~(v))
#define SET8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) | (v))
PUT8(dev, CONC_bSKIPC_OFF, 0x10);
PUT8(dev, CONC_bSKIPC_OFF, 0x10);
PUT8(dev, CONC_bSERFMT_OFF, tmp);
PUT8(dev, CONC_bINTSUMM_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bUARTCSTAT_OFF, 0x00);
PUT8(dev, CONC_bMISCCTL_OFF, tmp | CONC_MISCCTL_SYNC_RES);
PUT8(dev, CONC_bMISCCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bSERCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
#define CLR8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) & ~(v))
#define SET8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) | (v))
PUT8(dev, CONC_bSKIPC_OFF, 0x10);
PUT8(dev, CONC_bSERFMT_OFF, tmp);
PUT8(dev, CONC_bSERFMT_OFF, tmp);
PUT8(dev, CONC_bSKIPC_OFF, 0x10);
PUT8(dev, CONC_bSERFMT_OFF, tmp);
PUT8(dev, CONC_bDEVCTL_OFF, tmp);
PUT8(dev, CONC_bUARTCSTAT_OFF, 0x00);
PUT8(dev, CONC_bNMIENA_OFF, 0);
PUT8(dev, CONC_bSERCTL_OFF, 0);
PUT8(dev, CONC_bSERFMT_OFF,
PUT8(REG_TXSTATUS, 0);
PUT8(REG_TXFREETHRESH, 6);
PUT8(W2_STATION_ADDRESS + i, sc->ex_curraddr[i]);
PUT8(W2_STATION_MASK + i, 0);
PUT8(ip, CSR_CMD, RUC_START);
PUT8(ip, CSR_INTCTL, 0);
PUT8(ip, CSR_CMD, CUC_STATSBASE);
PUT8(ip, CSR_CMD, CUC_STATS_RST);
PUT8(ip, CSR_STS, sts);
PUT8(ip, CSR_CMD, RUC_START);
PUT8(ip, CSR_INTCTL, INTCTL_MASK);
PUT8(ip, CSR_INTCTL, INTCTL_MASK);
PUT8(ip, CSR_CMD, CUC_NOP);
PUT8(ip, CSR_CMD, CUC_RESUME);
PUT8(ip, CSR_INTCTL, INTCTL_MASK);
PUT8(ip, CSR_INTCTL, INTCTL_MASK);
PUT8(ip, CSR_CMD, CUC_CUBASE);
PUT8(ip, CSR_CMD, RUC_RUBASE);
PUT8(ip, CSR_CMD, CUC_START);
PUT8(ss, REG_TIMEOUT_CONTROL, ss->ss_tmoutclk);
PUT8(ss, REG_POWER_CONTROL, POWER_CONTROL_18V);
PUT8(ss, REG_POWER_CONTROL, POWER_CONTROL_18V |
PUT8(ss, REG_POWER_CONTROL, POWER_CONTROL_30V);
PUT8(ss, REG_POWER_CONTROL, POWER_CONTROL_30V |
PUT8(ss, REG_POWER_CONTROL, POWER_CONTROL_33V);
PUT8(ss, REG_POWER_CONTROL, POWER_CONTROL_33V |
PUT8(ss, REG_POWER_CONTROL, 0);
#define CLR8(ss, reg, mask) PUT8(ss, reg, GET8(ss, reg) & ~(mask))
#define SET8(ss, reg, mask) PUT8(ss, reg, GET8(ss, reg) | (mask))
#define PUTDATA8(ss, val) PUT8(ss, REG_DATA, val)
PUT8(ss, REG_SOFT_RESET, bits);