PUT16
PUT16(M1575_CPR_REG, data);
PUT16(M1575_CPR_REG+2, reg);
PUT16(M1575_CPR_REG+2, addr);
#define SET16(reg, bit) PUT16(reg, GET16(reg) | (bit))
#define CLR16(reg, bit) PUT16(reg, GET16(reg) & ~(bit))
PUT16(dev, port->reg_bufsz, (port->bufsz / 4) - 1);
PUT16(dev, port->reg_fragsz, (port->bufsz / 4) - 1);
#define CLR16(dev, offset, v) PUT16(dev, offset, GET16(dev, offset) & ~(v))
#define SET16(dev, offset, v) PUT16(dev, offset, GET16(dev, offset) | (v))
PUT16(dev, CONC_wDAC1IC_OFF, port->iframes - 1);
PUT16(dev, CONC_wDAC2IC_OFF, port->iframes - 1);
PUT16(dev, CONC_wADCIC_OFF, port->iframes - 1);
#define CLR16(dev, offset, v) PUT16(dev, offset, GET16(dev, offset) & ~(v))
#define SET16(dev, offset, v) PUT16(dev, offset, GET16(dev, offset) | (v))
PUT16(dev, CONC_wCODECCTL_OFF, (addr << 8) | data);
PUT16(dev, CONC_wDACRATE_OFF, audiopci_dac_rate(48000));
PUT16(dev, CONC_wDACIC_OFF, port->nframes - 1);
PUT16(dev, CONC_wSYNIC_OFF, port->nframes - 1);
PUT16(dev, CONC_wDACRATE_OFF, audiopci_dac_rate(48000));
PUT16(dev, CONC_wADCIC_OFF, port->nframes - 1);
PUT16(dev, CONC_wDACRATE_OFF, audiopci_dac_rate(48000));
PUT16(dev, CONC_wNMISTAT_OFF, 0);
PUT16(W0_EE_CMD, EE_CMD_READ | (offset & 0x3f));
PUT16(W4_PHYSMGMT, PHYSMGMT_DIR);
PUT16(W4_PHYSMGMT, val);
PUT16(W4_PHYSMGMT, val | PHYSMGMT_CLK);
PUT16(W4_PHYSMGMT, val);
PUT16(W4_PHYSMGMT, PHYSMGMT_DATA | PHYSMGMT_DIR);
PUT16(W4_PHYSMGMT, PHYSMGMT_DATA | PHYSMGMT_DIR | PHYSMGMT_CLK);
PUT16(W4_PHYSMGMT, PHYSMGMT_DATA | PHYSMGMT_DIR);
PUT16(W4_PHYSMGMT, 0); /* switch to input */
PUT16(W4_PHYSMGMT, PHYSMGMT_CLK); /* turnaround time */
PUT16(W4_PHYSMGMT, 0);
PUT16(W4_PHYSMGMT, PHYSMGMT_CLK); /* idle time */
PUT16(W4_PHYSMGMT, 0);
PUT16(W4_PHYSMGMT, PHYSMGMT_CLK);
PUT16(W4_PHYSMGMT, 0);
PUT16(W4_PHYSMGMT, PHYSMGMT_DIR);
PUT16(W4_PHYSMGMT, PHYSMGMT_DIR);
PUT16(W3_MAC_CONTROL, mctl);
PUT16(W3_MAX_PKT_SIZE, EX_BUFSZ);
PUT16(W3_MAC_CONTROL, GET16(W3_MAC_CONTROL) |
PUT16(W4_MEDIASTAT, 0);
PUT16(W4_MEDIASTAT,
PUT16(W4_MEDIASTAT, MEDIASTAT_LINKBEAT_EN);
PUT16(W4_MEDIASTAT, MEDIASTAT_SQE_EN);
PUT16(W3_MAC_CONTROL, mctl);
#define SET16(off, val) PUT16(off, GET16(off) | val)
#define CLR16(off, val) PUT16(off, GET16(off) & ~(val))
#define PUT_CMD(x) PUT16(REG_CMD_STAT, (x))
#define SET_WIN(x) PUT16(REG_CMD_STAT, CMD_SELECT_WINDOW | (x))
PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
PUT16(ip, CSR_EECTL, x | EEPROM_EESK | EEPROM_EECS);
PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
PUT16(ip, CSR_EECTL, EEPROM_EECS);
PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
PUT16(ip, CSR_EECTL, x | EEPROM_EESK | EEPROM_EECS);
PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
PUT16(ip, CSR_EECTL, EEPROM_EECS | EEPROM_EESK);
PUT16(ip, CSR_EECTL, EEPROM_EECS);
PUT16(ip, CSR_EECTL, 0);
PUT16(ss, REG_INT_STAT, INT_CMD);
PUT16(ss, REG_ERR_STAT, errs);
PUT16(ss, REG_BLKSZ, BLKSZ_BOUNDARY_512K | blksz);
PUT16(ss, REG_BLKSZ, blksz);
PUT16(ss, REG_BLOCK_COUNT, nblks);
PUT16(ss, REG_XFR_MODE, mode);
PUT16(ss, REG_COMMAND, command);
#define PUTDATA16(ss, val) PUT16(ss, REG_DATA, sw16(val))
PUT16(ss, REG_CLOCK_CONTROL, 0);
PUT16(ss, REG_CLOCK_CONTROL,
PUT16(ss, REG_CLOCK_CONTROL, val |
PUT16(ss, REG_CLOCK_CONTROL, CLOCK_CONTROL_INT_CLOCK_EN);
PUT16(ss, REG_INT_MASK, 0);
PUT16(ss, REG_INT_EN, 0);
PUT16(ss, REG_ERR_MASK, 0);
PUT16(ss, REG_ERR_EN, 0);
PUT16(ss, REG_INT_MASK, INT_MASK);
PUT16(ss, REG_INT_EN, INT_ENAB);
PUT16(ss, REG_ERR_MASK, ERR_MASK);
PUT16(ss, REG_ERR_EN, ERR_ENAB);
PUT16(ss, REG_COMMAND,
PUT16(ss, REG_INT_STAT, intr);
PUT16(ss, REG_INT_STAT, INT_DMA);
PUT16(ss, REG_INT_STAT, INT_RD);
PUT16(ss, REG_INT_STAT, INT_WR);
PUT16(ss, REG_INT_STAT, INT_XFR);
PUT16(ss, REG_ERR_STAT, errs);
PUT16(ss, REG_INT_STAT, INT_ERR);