PM_LEVEL_D0
case PM_LEVEL_D0:
(void) pm_raise_power(dip, 0, PM_LEVEL_D0);
if (ha->power_level != PM_LEVEL_D0) {
ha->power_level = PM_LEVEL_D0;
PM_LEVEL_D0) != DDI_SUCCESS) {
ha->power_level = PM_LEVEL_D0;
ql_halt(ha, PM_LEVEL_D0);
PM_LEVEL_D0) != DDI_SUCCESS) {
ha->power_level = PM_LEVEL_D0;
if (component != QL_POWER_COMPONENT || (level != PM_LEVEL_D0 &&
case PM_LEVEL_D0: /* power up to D0 state - fully on */
if (ha->power_level == PM_LEVEL_D0) {
ha->power_level = PM_LEVEL_D0;
if (ha->power_level != PM_LEVEL_D0) {
if (ha->power_level != PM_LEVEL_D0) {
if (ha->power_level != PM_LEVEL_D0) {
if (ha->power_level != PM_LEVEL_D0) {
ha->power_level != PM_LEVEL_D0) {
ASSERT(level == PM_LEVEL_D0 || level == PM_LEVEL_D3 ||
case PM_LEVEL_D0:
if (new_level < PM_LEVEL_D0 && !comp) {
if (new_level < PM_LEVEL_D0)
ASSERT(olevel >= PM_LEVEL_UNKNOWN && olevel <= PM_LEVEL_D0);
ASSERT(nlevel >= PM_LEVEL_UNKNOWN && nlevel <= PM_LEVEL_D0);
return (PM_LEVEL_D0);
if (pwr_p->pwr_func_lvl == PM_LEVEL_D0) {
if (pm_raise_power(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
PM_LEVEL_D0);
ASSERT(pwr_p->pwr_func_lvl == PM_LEVEL_D0);
ASSERT(pwr_p->pwr_func_lvl == PM_LEVEL_D0);
pwr_p->pwr_func_lvl != PM_LEVEL_D0) {
if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
PM_LEVEL_D0);
pwr_p->pwr_func_lvl = PM_LEVEL_D0;
if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 &&
((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) {
pwr_p->pwr_func_lvl = PM_LEVEL_D0;
pwr_p->pwr_func_lvl = PM_LEVEL_D0;
si_ctlp->sictl_power_level = PM_LEVEL_D0;
(void) pm_power_has_changed(dip, 0, PM_LEVEL_D0);
si_ctlp->sictl_power_level = PM_LEVEL_D0;
PM_LEVEL_D0);
case PM_LEVEL_D0: /* fully on */
si_ctlp->sictl_power_level = PM_LEVEL_D0;
if (mpt->m_power_level == PM_LEVEL_D0) {
rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
if (mpt->m_power_level != PM_LEVEL_D0) {
if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
mpt->m_power_level = PM_LEVEL_D0;
(mpt->m_power_level != PM_LEVEL_D0)) {
if (mpt->m_power_level != PM_LEVEL_D0) {
if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
case PM_LEVEL_D0:
mpt->m_power_level = PM_LEVEL_D0;
(mpt->m_power_level != PM_LEVEL_D0)) {
#define PCIE_D0_INDEX PM_LEVEL_D0
#define PCIE_UNKNOWN_INDEX PM_LEVEL_D0 + 1
ata_ctlp->ac_pm_level = PM_LEVEL_D0;
if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
if (ata_ctlp->ac_pm_level == PM_LEVEL_D0)
if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE)
ata_ctlp->ac_pm_level = PM_LEVEL_D0;
case PM_LEVEL_D0:
ata_ctlp->ac_pm_level = PM_LEVEL_D0;
if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) {
if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) !=
pwr_p->pwr_func_lvl = PM_LEVEL_D0;
case PM_LEVEL_D0:
case PM_LEVEL_D0: