PIL_15
rootnex_err_ibc = (ddi_iblock_cookie_t)PIL_15;
mutex_init(&cpu_idle_lock, NULL, MUTEX_SPIN, (void *)ipltospl(PIL_15));
cpc_level15_inum = add_softintr(PIL_15,
intr_enqueue_req(PIL_15, cpc_level15_inum);
mutex_init(&bfd_lock, NULL, MUTEX_SPIN, (void *)PIL_15);
} else if (spl == ipltospl(PIL_15)) {
intr_enqueue_req(PIL_15, cpc_level15_inum);
wr_clr_softint(1 << PIL_15);
PIL_15, /* System interrupt priority */
PIL_15, /* TOD interrupt priority */
PIL_15 /* Fan Fail priority */
sll %g2, PIL_15, %g2; \
mov PIL_15, %g4
cpc_level15_inum = add_softintr(PIL_15,
intr_enqueue_req(PIL_15, cpc_level15_inum);
mutex_init(&bfd_lock, NULL, MUTEX_SPIN, (void *)PIL_15);
mutex_init(&errh_print_lock, NULL, MUTEX_SPIN, (void *)PIL_15);
} else if (spl == ipltospl(PIL_15)) {
intr_enqueue_req(PIL_15, cpc_level15_inum);
wr_clr_softint(1 << PIL_15);