PHY_REG
PHY_REG(776, 20),
PHY_REG(776, 20), data);
PHY_REG(776, 20),
ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
PHY_REG(BM_PORT_CTRL_PAGE, 27),
#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
#define CV_SMB_CTRL PHY_REG(769, 23)
#define I218_ULP_CONFIG1 PHY_REG(779, 16)
#define HV_SMB_ADDR PHY_REG(768, 26)
#define HV_OEM_BITS PHY_REG(768, 25)
#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
#define HV_PM_CTRL PHY_REG(770, 17)
#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
#define I217_INBAND_CTRL PHY_REG(770, 18)
#define I217_LPI_GPIO_CTRL PHY_REG(772, 18)
#define I82579_LPI_CTRL PHY_REG(772, 20)
#define I82579_DFT_CTRL PHY_REG(769, 20)
#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
#define I217_CGFREG PHY_REG(772, 29)
#define I217_MEMPWR PHY_REG(772, 26)
(void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg);
(void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg);
(void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
(void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
(void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg);
(void) e1000_write_phy_reg(hw, PHY_REG(776, 16),
(void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
(void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
(void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg);
(void) e1000_write_phy_reg(hw, PHY_REG(769, 20),
(void) e1000_read_phy_reg(hw, PHY_REG(770, 26), &phy_data);
(void) e1000_write_phy_reg(hw, PHY_REG(770, 26), phy_data);